VSD – Mixed-signal RISC-V based SoC on FPGA

VSD – Mixed-signal RISC-V based SoC on FPGA, available at $39.99, has an average rating of 4, with 14 lectures, based on 7 reviews, and has 106 subscribers.

You will learn about FPGA flow vs ASIC flow Basic mixed-signal RISC-V based SoC RTL design and simulations FPGA Synthesis, bit-stream generation and simulation This course is ideal for individuals who are Beginner in FPGA design or Beginner in VLSI design or Experienced Physical Design and STA engineers It is particularly useful for Beginner in FPGA design or Beginner in VLSI design or Experienced Physical Design and STA engineers.

Enroll now: VSD – Mixed-signal RISC-V based SoC on FPGA

Summary

Title: VSD – Mixed-signal RISC-V based SoC on FPGA

Price: $39.99

Average Rating: 4

Number of Lectures: 14

Number of Published Lectures: 14

Number of Curriculum Items: 14

Number of Published Curriculum Objects: 14

Original Price: $199.99

Quality Status: approved

Status: Live

What You Will Learn

FPGA flow vs ASIC flow
Basic mixed-signal RISC-V based SoC RTL design and simulations
FPGA Synthesis, bit-stream generation and simulation

Who Should Attend

Beginner in FPGA design
Beginner in VLSI design
Experienced Physical Design and STA engineers

Target Audiences

Beginner in FPGA design
Beginner in VLSI design
Experienced Physical Design and STA engineers

This webinar helps you get started with a basic mixed-signal FPGA flow, which can be extended to any complex SoC.

VSD and RedwoodEDA conducts 5-day RISC-V based MYTH (Microprocessors for You in Thirty Hours) workshop using transaction level Verilog on Makerchip platform. For people who have done this workshop can use this webinar as an extension to the 5th Day, where RISC-V pipe-lined CPU coded in TL-Verilog is now converted to verilog language and is a part of a mixed-signal SoC

If you are from ASIC/Physical design back-ground, this webinar will complement your existing work, and you would really get to know similarities and differences between ASIC and FPGA flow, which one is preferred under what conditions and why is it preferred

This single webinar connects VLSI students, analog designers, FPGA designers and ASIC designers. It is also an attempt to bring everyone on the same platform, and serves as a starting point for design verification

Stay tuned for follow-up series of FPGA webinars and 5-day hands-on high intensity FPGA workshop, which will be built around OpenFPGA framework and Makerchip visualization software, that enables the whole community to learn FPGA fundamentals along with labs, without actually having a physical FPGA board.

Innovation at its best

All the best and happy learning

Course Curriculum

Chapter 1: Introduction

Lecture 1: Introduction

Chapter 2: Mixed Signal SoC details with RISC-V core and PLL IP

Lecture 1: RVMYTH RISC-V Core

Lecture 2: Transaction level Verilog

Lecture 3: Why FPGAs ?

Lecture 4: Makerchip platform

Lecture 5: TL – Verilog to RTL verilog

Lecture 6: Functional Simulation using iverilog

Chapter 3: Mixed Signal FPGA flow

Lecture 1: FPGA – Steps to create project

Lecture 2: FPGA – Steps to generate IPs

Lecture 3: FPGA – RTL simulation

Lecture 4: FPGA – Synthesis

Lecture 5: FPGA – Implementation and timing analysis

Lecture 6: FPGA – Bit-stream generation, FPGA programming and ILA

Chapter 4: Conclusion

Lecture 1: Conclusion and Assignment

Instructors

Kunal Ghosh
Digital and Sign-off expert at VLSI System Design(VSD)
Shivani Shah
Instructor

Rating Distribution

1 stars: 0 votes
2 stars: 1 votes
3 stars: 1 votes
4 stars: 3 votes
5 stars: 2 votes

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