VSD – Static Timing Analysis – I

Course Curriculum

Chapter 1: Introduction and agenda

Lecture 1: Introduction

Lecture 2: Introduction to timing path and arrival time

Lecture 3: Introduction to required time and slack

Lecture 4: Introduction to basic categories of setup and hold analysis

Lecture 5: Introduction to data check and latch timing

Lecture 6: Introduction to slew, load and clock checks

Chapter 2: First things first – Introduction to timing graph

Lecture 1: Convert logic gates into nodes

Lecture 2: Compute actual arrival time (AAT)

Lecture 3: Compute required arrival time (RAT)

Lecture 4: Compute slack and introduction to GBA-PBA analysis

Lecture 5: Convert pins to nodes and compute AAT, RAT and slack

Chapter 3: Clk-to-q delay, library setup, hold time and jitter

Lecture 1: Introduction to transistor level circuit for flops

Lecture 2: Negative and positive latch transistor level operation

Lecture 3: Library setup time calculation

Lecture 4: Clk-q delay calculation

Lecture 5: Steps to create eye diagram for jitter analysis

Lecture 6: Jitter extraction and accounting in setup timing analysis

Chapter 4: Textual timing reports and hold analysis

Lecture 1: Setup analysis – graphical to textual representation

Lecture 2: Hold analysis with real clocks

Lecture 3: Hold analysis – graphical to textual representation

Chapter 5: On-chip variation

Lecture 1: Sources of variation – etching

Lecture 2: Sources of variation – oxide thickness

Lecture 3: Relationship between resistance, drain current and delay

Chapter 6: OCV timing and pessimism removal

Lecture 1: OCV based setup timing analysis

Lecture 2: Setup timing analysis after pessimism removal

Lecture 3: OCV based hold timing analysis

Lecture 4: Hold timing analysis after pessimism removal

Chapter 7: Conclusion

Lecture 1: Conclusion and next topics!!