VSD – Pipelining RISC-V with Transaction-Level Verilog

VSD – Pipelining RISC-V with Transaction-Level Verilog, available at $34.99, has an average rating of 4.55, with 27 lectures, based on 88 reviews, and has 717 subscribers.

You will learn about Students will be able to use and implement concepts of pipelining using TL-verilog language and Makerchip platform Build their own verilog models for IP's using a simpler and powerful Verilog design environment This course is ideal for individuals who are Anyone who wants to learn transaction-level verilog or Anyone who wants to stay ahead of curve in frontend VLSI or Anyone who wants to learn and implement pipelining concepts in field of computer architecture It is particularly useful for Anyone who wants to learn transaction-level verilog or Anyone who wants to stay ahead of curve in frontend VLSI or Anyone who wants to learn and implement pipelining concepts in field of computer architecture.

Enroll now: VSD – Pipelining RISC-V with Transaction-Level Verilog

Summary

Title: VSD – Pipelining RISC-V with Transaction-Level Verilog

Price: $34.99

Average Rating: 4.55

Number of Lectures: 27

Number of Published Lectures: 27

Number of Curriculum Items: 27

Number of Published Curriculum Objects: 27

Original Price: $84.99

Quality Status: approved

Status: Live

What You Will Learn

Students will be able to use and implement concepts of pipelining using TL-verilog language and Makerchip platform
Build their own verilog models for IP's using a simpler and powerful Verilog design environment

Who Should Attend

Anyone who wants to learn transaction-level verilog
Anyone who wants to stay ahead of curve in frontend VLSI
Anyone who wants to learn and implement pipelining concepts in field of computer architecture

Target Audiences

Anyone who wants to learn transaction-level verilog
Anyone who wants to stay ahead of curve in frontend VLSI
Anyone who wants to learn and implement pipelining concepts in field of computer architecture

Do you want to build just verilog models or high-quality verilog models in half the time?�

Have you implemented a processor using Verilog? Which was the most important part of your implementation? What was your code size in Verilog? What if, we told you that you can reduce your verilog code size by about 3.5x by a new technology? What if, we told you that you can create any digital sequential logic you can dream up faster than you ever thought possible, all within your browser?

How about a ‘change’? Change the way you used to write your verilog code. Change the way you used to implement Pipelining for your processor. Change is the only “constant”. I encourage and welcome you to think in the right direction with experts from this field in my webinar on “Pipelining RISC-V with Transaction-Level Verilog” which was conducted on 10th Feb’ 2018 with Steve Hoover, Founder of Redwood EDA and Makerchip Platform

This webinar is really important for people
who have taken up my RISC-V ISA course on Udemy, as we will show
efficient RTL implementation of some instructions in this
one.

Enjoy the webinar and Happy Learning….

Course Curriculum

Chapter 1: Introduction

Lecture 1: Introduction and welcome to participants and Steve

Lecture 2: Launch of makerchip.com and introduction to webinar motive

Lecture 3: Live QnA with participants on webinar content and motive

Chapter 2: RISC-V overview and instruction Pipelining Concepts

Lecture 1: Pipelined RISC-V block diagram description

Lecture 2: RISC-V waterfall diagram and hazards

Lecture 3: Live QnA with participants regarding processor architecture

Chapter 3: IP design methodology

Lecture 1: RISC-V IP challenges and WARP-V development progress

Lecture 2: Why Transaction-Level verilog?

Lecture 3: Introduction to makerchip.com platform

Chapter 4: Examples using makerchip.com platform

Lecture 1: More about makerchip.com and first exercise for participants

Lecture 2: Inverter exercise for participants and LIVE QnA about makerchip.com platform

Lecture 3: Sequential logic – Fibonacci series example

Lecture 4: LIVE QnA with participants regarding exercises

Chapter 5: Pipelines

Lecture 1: Pythagoras theorem example of pipeline

Lecture 2: Retiming implementation in TL-Verilog vs system verilog

Lecture 3: Fibonnaci series pipeline and concept of validity

Lecture 4: Exercise to identify error conditions in WARP-V

Chapter 6: Pipeline Interactions

Lecture 1: WARP-V operand mux

Lecture 2: Register bypass and time division multiplexing (TDM) example

Lecture 3: Solve TDM exercise – Part1

Lecture 4: Solve TDM exercise – Part2

Lecture 5: LIVE QnA with participants regarding pipeline interactions and other topics

Chapter 7: Miscellaneous Topics

Lecture 1: Hierarchy and interfaces in TL-Verilog

Lecture 2: LIVE QnA with participants on WARP-V core

Lecture 3: Transaction flow and wrap-up course content

Chapter 8: Certification challenge and conclusion

Lecture 1: Certification challenge problem statement

Lecture 2: Conclusion

Instructors

Kunal Ghosh
Digital and Sign-off expert at VLSI System Design(VSD)
Steven Hoover
Founder, Redwood EDA

Rating Distribution

1 stars: 4 votes
2 stars: 5 votes
3 stars: 12 votes
4 stars: 23 votes
5 stars: 44 votes

Frequently Asked Questions

How long do I have access to the course materials?

You can view and review the lecture materials indefinitely, like an on-demand channel.

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