VSD – Library characterization and modelling – Part 1

Course Curriculum

Chapter 1: Introduction

Lecture 1: Introduction and Acknowledgements

Lecture 2: Need for characterization

Chapter 2: Cell design and characterization flows

Lecture 1: Inputs for cell design flow

Lecture 2: Circuit design step

Lecture 3: Layout design step

Lecture 4: Typical characterization flow

Chapter 3: General Timing characterization parameters

Lecture 1: Timing threshold definitions

Lecture 2: Propagation delay and transition time

Lecture 3: Output current model and CCS table

Lecture 4: Output voltage waveform and introduction to tristate buffer

Lecture 5: Different transitions for tristate buffer

Chapter 4: Timing characterization parameters for registers

Lecture 1: Netlist connectivity for latch and flipflop

Lecture 2: Library setup time as a function of data and clock transition time

Lecture 3: True single phase clocked (TSPC) register for hold time evaluation

Lecture 4: Library setup time for TSPC register

Lecture 5: Hold time, recovery & removal time evaluation

Chapter 5: Noise characterization and modelling

Lecture 1: Introduction to noise – Crosstalk glitch and delta delay

Lecture 2: Introduction to channel connected components (CCC)

Lecture 3: ccsn_first_stage, ccsn_last_stage and VIVO model based dc_current

Lecture 4: Need of dc_current attribute

Lecture 5: Noise immunity curve, propagated_noise_high and propagated_noise_low

Lecture 6: stage_type attribute and need for tie_hi cells

Lecture 7: Miller cap, arc based ccs noise model and full noise library

Chapter 6: Power characterization and modelling

Lecture 1: Static power – Subthreshold current and junction leakage current

Lecture 2: Static power – Tunnelling current

Lecture 3: Internal leakage power – leakage_current and leakage_power groups

Lecture 4: Internal leakage power – cell_leakage_power & Tunneling curent – gate_leakage

Lecture 5: Dynamic power – Switching current

Lecture 6: Dynamic power – Short-circuit current

Lecture 7: Switching power and short-circuit power modelling

Lecture 8: Hidden power concept and modelling

Chapter 7: Timing modelling

Lecture 1: Groups and attributes

Lecture 2: Library group and its attributes

Lecture 3: Cell groups and combinational function pin groups

Lecture 4: Flip-flop modelling using 'ff' group

Lecture 5: Latch modelling using 'latch' group

Lecture 6: Introduction to 'statetable' and latch description using 'statetable' group

Lecture 7: Flip-flop modelling using 'statetable' group and introduction to 'driver model'

Chapter 8: Conclusion

Lecture 1: Driver model, receiver model and conclusion