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Embedded System Design with Xilinx ZYNQ SoC and SDK

IT & Software

Embedded System Design with Xilinx ZYNQ SoC and SDK, available at $59.99, has an average rating of 4.25, with 132 lectures, based on 85 reviews, and has 662 subscribers.

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You will learn about Embedded System Design flow using Zynq AP SoC Development of C applications for Zynq Devices Fundamentals strategies to use Xilinx Drivers Software and Hardware Debugging Strategies Software Profiling Working with Interrupts This course is ideal for individuals who are Anyone wish to build expertise in Xilinx Zynq APSOC and Xilinx SDK Environment or Embedded System Design with FPGA Processors It is particularly useful for Anyone wish to build expertise in Xilinx Zynq APSOC and Xilinx SDK Environment or Embedded System Design with FPGA Processors.

Enroll now: Embedded System Design with Xilinx ZYNQ SoC and SDK

Summary

Title: Embedded System Design with Xilinx ZYNQ SoC and SDK

Price: $59.99

Average Rating: 4.25

Number of Lectures: 132

Number of Published Lectures: 132

Number of Curriculum Items: 132

Number of Published Curriculum Objects: 132

Original Price: ₹1,199

Quality Status: approved

Status: Live

What You Will Learn

  • Embedded System Design flow using Zynq AP SoC
  • Development of C applications for Zynq Devices
  • Fundamentals strategies to use Xilinx Drivers
  • Software and Hardware Debugging Strategies
  • Software Profiling
  • Working with Interrupts

Who Should Attend

  • Anyone wish to build expertise in Xilinx Zynq APSOC and Xilinx SDK Environment
  • Embedded System Design with FPGA Processors

Target Audiences

  • Anyone wish to build expertise in Xilinx Zynq APSOC and Xilinx SDK Environment
  • Embedded System Design with FPGA Processors

Xilinx Zynq SoC’s are know to provide maximum performance per watt along with maximum reconfiguration flexibility. Zynq family features Dual-Core ARM Cortex A9 processors tightly coupled with the 7-series FPGA to enable faster communication interfaces development with ARM Design flow and hardware acceleration. Zynq devices are available in two categories viz. Zynq-7000s family FPGA for the cost-effective application such as IoT related applications while Zynq 7000 family FPGA are best for high-performance applications such as Embedded Vision etc. The Zynq 7000s comes with Single core ARM while Zynq 7000 comes with Dual-Core ARM.

This course covers fundamentals of Popular Xilinx drivers viz. UART, AXI Timers, UART16550, AXI GPIO, AXI BRAM, etc. The course also illustrates the usage of the AXI interrupt controller for handling Interrupts. Also to felicitate incorporation of Hardware accelerators with Zynq based design few examples on building Custom AXI Peripherals are also included. Software and Hardware Debugging, Profiling fundamentals are demonstrated with Zynq to felicitate performance measurement.

This course will create the foundation necessary to quickly start building applications on Zynq FPGA devices without prior experience in this domain.  The entire course is a Lab-based course with a major focussed on building skills necessary to handle simple peripherals such as GPIO, Intermediate Peripherals such as UART PS, AXI BRAM, and complex Peripherals such as AXI Interrupt Controller,  AXI Timers, GIC etc.

Course Curriculum

Chapter 1: Installing Vivado

Lecture 1: Course Framework

Lecture 2: Agenda

Lecture 3: Tools used in the course

Lecture 4: Recommendation

Lecture 5: Installation Part 1

Lecture 6: Installation Part 2

Lecture 7: Xilinx LIC file

Lecture 8: Adding Licencse

Lecture 9: Digilent Board files: Download this before proceeding to the next Video

Lecture 10: Adding Digilent Boards and Hardware Connection

Chapter 2: Toolchain Configuration

Lecture 1: Agenda

Lecture 2: Introduction P1

Lecture 3: Introduction P2

Lecture 4: Code and BD

Lecture 5: Fundamental P1 : Project Types

Lecture 6: Fundamentals P2 : Flow Navigator

Lecture 7: Fundamentals P3 : Board Presets

Lecture 8: Fundamentals P4 : When you need to add I/O Constraint

Lecture 9: Fundantals P5 : When you need to add I/O Constriaints

Lecture 10: Understanding useful Files added to Project Directory

Lecture 11: How to use TCL Script for BD automation

Lecture 12: Fundamentals of SDK P1

Lecture 13: Fundamentals of SDK P2

Lecture 14: Fundamentals of Reporting Mechanism

Chapter 3: Getting Started with Simple Peripherals : GPIO

Lecture 1: Agenda

Lecture 2: Zynq Intro

Lecture 3: Zynq Peripherals

Lecture 4: Ways to Communicate data between PS and Peripherals P1

Lecture 5: Ways to Communicate data between PS and Peripherals P2

Lecture 6: Fundamentals of XIL Drivers P1

Lecture 7: Fundamentals of XIL Drivers P2

Lecture 8: Fundamentals of XIL Drivers P3

Lecture 9: Demonstration of XIL Drivers

Lecture 10: Using MIO LED P1

Lecture 11: Using MIO LED P2

Lecture 12: C Code : MIO LED

Lecture 13: Using MIO GPIO Input and Output

Lecture 14: C Code : MIO BTN AND LED

Lecture 15: Using GPIO EMIO LED P1

Lecture 16: Using GPIO EMIO LED P2

Lecture 17: ZYNQ EMIO LED C Code

Lecture 18: Using GPIO EMIO LED AND BTN P1

Lecture 19: Using GPIO EMIO LED AND BTN P2

Lecture 20: Code: GPIO LED and SWITCH

Lecture 21: Using AXI GPIO IP :Single Channel P1

Lecture 22: Using AXI GPIO IP :Single Channel P2

Lecture 23: CODE: AXI GPIO Single Channel

Lecture 24: Using AXI GPIO IP : Multiple Channels P1

Lecture 25: Using AXI GPIO IP : Multiple Channels P2

Lecture 26: Code

Chapter 4: Getting started with Intermediate Drivers : UARTPS

Lecture 1: Agenda

Lecture 2: Overview

Lecture 3: UART with MIO P1

Lecture 4: UART with MIO P2

Lecture 5: UART with MIO P3

Lecture 6: Code : UART MIO

Lecture 7: MIO : Using UART0 and PMOD to extend Capabilities

Lecture 8: EMIO : Performing connection to External Hardware / PL to UART

Lecture 9: EMIO : Using AXI UARTLITE P1

Lecture 10: EMIO : Using AXI UARTLITE P2

Lecture 11: EMIO : Using AXI UARTLITE P3

Chapter 5: Getting started with Intermediate Drivers : Understanding Timers

Lecture 1: Agenda

Lecture 2: Timers/Counters in Zynq Processing System

Lecture 3: CPU Watchdog Timer P1

Lecture 4: CPU Watchdog Timer P2

Lecture 5: CPU Watchdog Timer P3

Lecture 6: Code

Lecture 7: CPU 32-bit Private Timer

Lecture 8: Code

Lecture 9: CPU 32-bit Timer : Use of Auto-reload Mode

Lecture 10: Code

Lecture 11: CPU 32-bit Timer : Use of Prescalar

Lecture 12: Code

Lecture 13: TTC in Polled Mode P1

Lecture 14: TTC in Polled Mode P2

Lecture 15: TTC in Polled Mode P3

Lecture 16: Code

Lecture 17: TTC and GPIO MIO LED in Polled Mode

Lecture 18: Code

Lecture 19: Working with PL Timer : AXI Timer IP P1

Lecture 20: Working with PL Timer : AXI Timer IP P2

Lecture 21: Code

Chapter 6: Software and Hardware Debugging

Lecture 1: Agenda

Lecture 2: Using Serial Window for Debugging

Lecture 3: Breakpoint P1

Lecture 4: Breakpoint P2

Lecture 5: Breakpoint P3

Lecture 6: Breakpoint P4

Lecture 7: Breakpoint P5

Lecture 8: Using Memory Content Viewer

Lecture 9: Using XSCT Console

Lecture 10: ILA : Using ILA Probe P1

Lecture 11: ILA : Using ILA Probe P2

Lecture 12: ILA P1

Instructors

Rating Distribution

  • 1 stars: 3 votes
  • 2 stars: 3 votes
  • 3 stars: 9 votes
  • 4 stars: 24 votes
  • 5 stars: 46 votes

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