Communication Series P1 : UART, SPI and I2C in Verilog

Communication Series P1 : UART, SPI and I2C in Verilog, available at $69.99, has an average rating of 4.27, with 94 lectures, based on 80 reviews, and has 849 subscribers.

You will learn about Essential principles of UART, SPI, and I2C. Implementation of UART 16550A, PMOD DA4. Different Modes of SPI, Daisy Chain Configuration of SPI. Bit Banging This course is ideal for individuals who are A VLSI engineer is interested in constructing the foundational elements of the standard communication interfaces frequently utilized in FPGA systems. It is particularly useful for A VLSI engineer is interested in constructing the foundational elements of the standard communication interfaces frequently utilized in FPGA systems.

Enroll now: Communication Series P1 : UART, SPI and I2C in Verilog

Summary

Title: Communication Series P1 : UART, SPI and I2C in Verilog

Price: $69.99

Average Rating: 4.27

Number of Lectures: 94

Number of Published Lectures: 94

Number of Curriculum Items: 97

Number of Published Curriculum Objects: 97

Original Price: ₹1,799

Quality Status: approved

Status: Live

What You Will Learn

Essential principles of UART, SPI, and I2C.
Implementation of UART 16550A, PMOD DA4.
Different Modes of SPI, Daisy Chain Configuration of SPI.
Bit Banging

Who Should Attend

A VLSI engineer is interested in constructing the foundational elements of the standard communication interfaces frequently utilized in FPGA systems.

Target Audiences

A VLSI engineer is interested in constructing the foundational elements of the standard communication interfaces frequently utilized in FPGA systems.

This comprehensive course is meticulously designed to cater to a broad audience, ranging from beginners who are just stepping into the world of digital design and hardware description languages (HDLs) to experienced FPGA/ASIC developers looking to deepen their expertise. The central aim of this course is to equip participants with a thorough mastery of digital communication interfaces, employing Verilog as the primary tool. Regardless of your prior experience in the field, this course offers something valuable. Beginners will find a structured and gradual introduction to the complex world of digital communication interfaces and Verilog. The course spans a comprehensive curriculum that encompasses three fundamental digital communication protocols: Serial Peripheral Interface (SPI), Universal Asynchronous Receiver-Transmitter (UART), and Inter-Integrated Circuit (I2C). Each of these protocols plays a critical role in modern electronics and embedded systems, and mastering them is vital for both aspiring and experienced engineers.

In summary, this course is a transformative journey that welcomes participants at all skill levels into the world of digital communication interfaces and Verilog. It equips you with the skills, knowledge, and confidence needed to excel in the dynamic and ever-evolving field of digital design and embedded systems. Whether you’re taking your first steps or seeking to advance your career, this course provides a robust foundation for your success.

Course Curriculum

Chapter 1: UART

Lecture 1: Communication Series Overview

Lecture 2: Interfaces Classification

Lecture 3: Overview

Lecture 4: Simple UART TX

Lecture 5: Simple UART RX

Lecture 6: Simple UART TB

Lecture 7: Design Code

Lecture 8: TB Code

Lecture 9: UART 16550A Overview

Lecture 10: UART 16550 : FIFO P1

Lecture 11: UART 16550 : FIFO P2

Lecture 12: UART 16550 : FIFO P3

Lecture 13: UART 16550 : FIFO P4

Lecture 14: FIFO TB

Lecture 15: Design Code

Lecture 16: Testbench Code

Lecture 17: UART 16550 TX : Understanding Oversampling in Baud Generator

Lecture 18: UART 16550 TX : LCR (Line Control Register)

Lecture 19: UART 16550 TX : Stop bits

Lecture 20: UART 16550 TX : TX Logic

Lecture 21: UART 16550 TX : TX TB

Lecture 22: Design Code

Lecture 23: TB Code

Lecture 24: UART 16550 RX : RX Logic

Lecture 25: UART 16550 RX : RX TB

Lecture 26: Design Code

Lecture 27: TB Code

Lecture 28: UART 16550 Registers : Overview

Lecture 29: UART 16550 Registers : THR and RBR

Lecture 30: UART 16550 Registers : Divisor Latch

Lecture 31: UART 16550 Registers : FCR and LCR

Lecture 32: UART 16550 Registers : LSR

Lecture 33: UART 16550 Registers : TB

Lecture 34: Design Code

Lecture 35: TB Code

Lecture 36: Complete Design

Lecture 37: TX testbench

Lecture 38: Design Code

Lecture 39: TB Code

Chapter 2: SPI

Lecture 1: Overview

Lecture 2: Understanding SPI Protocol P1

Lecture 3: Understanding SPI Protocol P2

Lecture 4: Understanding SPI Protocol P3

Lecture 5: SPI protocol without different mode

Lecture 6: SPI Master P1

Lecture 7: SPI Master P2

Lecture 8: SPI Master P3

Lecture 9: Code

Lecture 10: SPI Slave P1

Lecture 11: SPI Slave P2

Lecture 12: Code

Lecture 13: Alternate Implementation

Lecture 14: Code

Lecture 15: Understanding CPOL behavior

Lecture 16: Implementation

Lecture 17: Code

Lecture 18: Understanding CPHA

Lecture 19: Understanding SPI Modes with different CPOL and CPHA

Lecture 20: Working with CPHA Master

Lecture 21: Master TB

Lecture 22: Code

Lecture 23: Working with CPHA Slave

Lecture 24: Code

Lecture 25: Digilent PMOD DA4 (Analog Devices AD5628) : Understanding Specifications

Lecture 26: Digilent PMOD DA4 (Analog Devices AD5628) : Master Design

Lecture 27: Digilent PMOD DA4 (Analog Devices AD5628) : TB

Lecture 28: Design Code

Lecture 29: TB Code

Lecture 30: Daisy Chain Configuration

Lecture 31: Master

Lecture 32: Slave

Lecture 33: Testbench

Lecture 34: Design Code

Lecture 35: TB Code

Lecture 36: One Notes

Chapter 3: I2C

Lecture 1: Overview

Lecture 2: Understanding I2C Open Drain Interface

Lecture 3: Start and Stop Conditions

Lecture 4: I2C Write and Read Transactions

Lecture 5: I2C Master FSM without Clock Stretch

Lecture 6: I2C Master without clock stretch

Lecture 7: Master TB

Lecture 8: Design Code

Lecture 9: TB Code

Lecture 10: I2C Slave without clock stretch

Lecture 11: Testbench for top

Lecture 12: Design Code

Lecture 13: TB Code

Lecture 14: Bit Banging

Lecture 15: Understanding Clock Stretching

Lecture 16: Implementation of Master

Lecture 17: Implementation of Slave

Lecture 18: Design Code

Lecture 19: TB Code

Instructors

Kumar Khandagle
Trainer @ NAMASTE FPGA

Rating Distribution

1 stars: 3 votes
2 stars: 1 votes
3 stars: 9 votes
4 stars: 33 votes
5 stars: 34 votes

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