VSD – Embedded-UVM

VSD – Embedded-UVM, available at $39.99, has an average rating of 3.85, with 29 lectures, based on 16 reviews, and has 164 subscribers.

You will learn about We take a dive into Embedded UVM and its use cases as a platform for Functional Verification and SoC FPGA based Emulation We learn how to code Embedded UVM powered testbench for a hardware accelerator design IP The test bench is then adapted to Cyclone V and Ultrascale Zynq based platforms to demonstrate Embedded UVM powered low-cost SoCFPGA based emulation solutions. This course is ideal for individuals who are Freshers and experienced in UVM keen to know about opensource Embedded-UVM technology or Professional UVM engineers keen to know about multi-threaded testbench simulation technology or Anyone looking to learn new opensource technology and be ahead of market It is particularly useful for Freshers and experienced in UVM keen to know about opensource Embedded-UVM technology or Professional UVM engineers keen to know about multi-threaded testbench simulation technology or Anyone looking to learn new opensource technology and be ahead of market.

Enroll now: VSD – Embedded-UVM

Summary

Title: VSD – Embedded-UVM

Price: $39.99

Average Rating: 3.85

Number of Lectures: 29

Number of Published Lectures: 29

Number of Curriculum Items: 29

Number of Published Curriculum Objects: 29

Original Price: $84.99

Quality Status: approved

Status: Live

What You Will Learn

We take a dive into Embedded UVM and its use cases as a platform for Functional Verification and SoC FPGA based Emulation
We learn how to code Embedded UVM powered testbench for a hardware accelerator design IP
The test bench is then adapted to Cyclone V and Ultrascale Zynq based platforms to demonstrate Embedded UVM powered low-cost SoCFPGA based emulation solutions.

Who Should Attend

Freshers and experienced in UVM keen to know about opensource Embedded-UVM technology
Professional UVM engineers keen to know about multi-threaded testbench simulation technology
Anyone looking to learn new opensource technology and be ahead of market

Target Audiences

Freshers and experienced in UVM keen to know about opensource Embedded-UVM technology
Professional UVM engineers keen to know about multi-threaded testbench simulation technology
Anyone looking to learn new opensource technology and be ahead of market

Of course, there is a requirement for open-source verification, but that’s not the only thing we want to cater to. There are other verification trends and challenges which system Verilog and other verification platforms are not able to meet. So, we want to position Embedded-UVM for that. In the past decade or so, the major thing which is making verification tougher than it used to be, is the death of Moore’s law.

As far as processor frequency goes, it stabilizes at 4GHz and it’s coming down as we move to multi-core processors. So, when you look at it from a simulation perspective, post-2005 it is becoming increasingly difficult to run simulations on bigger chips.

Chip size keeps increasing, while processor speed is stagnant and hence, simulation is a limiting factor. Simulation speed is going to be limited unless we move to multi-core processors. Contemporary EDA tools run RTL simulations in a multi-core environment. System Verilog doesn’t run in a multi-core environment.

Therefore, test-bench runs on one thread and RTL runs on multiple threads. RTL is more formal in nature, in sense, it can be synthesized, it can be partitioned, different partitions can run on different processors, while test-bench is behavioral in nature and it cannot be partitioned the way RTL can be.

About Speaker:

Puneet Goel is a 1994 graduate in Electronics from Punjab Engineering College. He has 24 years of experience in the VLSI industry where he worked for STMicro, Motorola, Texas Instruments and TranSwitch.

For the past 8 years, he has been working for Coverity Systems Technology, where he provides verification services and works on creating viable opensource solutions for chip verification. Puneet is the main developer of Embedded UVM.

Course Curriculum

Chapter 1: Introduction

Lecture 1: Introduction

Lecture 2: Introduction to FPGA boards to be used in webinar

Lecture 3: Introduction to E-UVM framework using adder example

Lecture 4: Testcase and E-UVM download links

Chapter 2: Verification trends and challenges

Lecture 1: Verification perfomance and introduction to FOSSI

Lecture 2: Variation trends and challenges of data network and compute performance

Lecture 3: Testbenches for system level verification and hardware accelerators

Lecture 4: Hardware accelerators from verification perspective

Lecture 5: Hardware accelerators perspective Embedded – UVM

Lecture 6: LIVE QnA with participants about E-UVM multi-threading

Lecture 7: LIVE QnA regarding system-C comparison with E-UVM

Chapter 3: Embedded UVM and Multicore testbenches

Lecture 1: Introduction to Embedded-UVM

Lecture 2: Embedded-UVM innovation – Multicore UVM

Lecture 3: Multicore E-UVM implementation

Chapter 4: Productivity and Emulation Features

Lecture 1: Productivity features and interfacing with RTL simulations

Lecture 2: Embedded UVM powered emulation

Lecture 3: Testbench simulation demo with Avalon streaming bus as DUT

Lecture 4: OSI model of communication and UVM transaction explanation

Chapter 5: Embedded UVM Testbench Architecture and Environment

Lecture 1: Testbench architecture and verilog co-simulation

Lecture 2: Steps and importance of Randomizing object and cloning

Lecture 3: Typical UVM environment comparison in Embedded-UVM and system verilog

Lecture 4: LIVE QnA with webinar participants regarding E-UVM environment

Lecture 5: avst_keccak protocol

Chapter 6: The DUT – SHA3 core

Lecture 1: Functional details, control & status, data map, output and input

Lecture 2: SHA3 core testbench understanding and running

Lecture 3: LIVE demo on DE10-Nano Cyclone V FPGA board

Lecture 4: LIVE code debug and emulation

Chapter 7: Assignments and Conclusion

Lecture 1: Assignment explanation and conclusion

Lecture 2: Assignment testcase download links

Instructors

Kunal Ghosh
Digital and Sign-off expert at VLSI System Design(VSD)
Puneet Goel
CTO at Coverify

Rating Distribution

1 stars: 1 votes
2 stars: 0 votes
3 stars: 3 votes
4 stars: 8 votes
5 stars: 4 votes

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