SystemVerilog Assertions & Functional Coverage FROM SCRATCH

Course Curriculum

Chapter 1: Welcome and introduction to SystemVerilog Assertions

Lecture 1: Welcome and introduction to SystemVerilog Assertions

Lecture 2: What is an Assertion? What are the benefits? Project wide methodology guidelines

Chapter 2: Immediate Assertions

Lecture 1: Types of assertions, Immediate and Deferred immediate assertions

Chapter 3: Concurrent Assertions – Basics

Lecture 1: Sequence, Property, Assert and Cover. Implication Operator (Overlapping, Non-ove

Lecture 2: Vacuous PASS

Lecture 3: Clocking basics (singly clocked properties)

Lecture 4: Multi-threading, Formal arguments, disable iff and severity levels

Lecture 5: Binding properties

Chapter 4: Concurrent Assertions – Sampled Value Function

Lecture 1: Sampled value Functions (PART 1): $rose, $fell

Lecture 2: Sampled Value Functions (PART 2) : $stable, $past, $changed, $sampled

Chapter 5: Concurrent Assertions – Operators

Lecture 1: Clock delay operator

Lecture 2: Consecutive repetition

Lecture 3: Non-consecutive repetition, Non-consecutive GoTo

Lecture 4: ‘throughout’, ‘within’

Lecture 5: ‘and’, ‘or’, ‘intersect’

Lecture 6: 'and', 'or', 'intersect – further nuances

Lecture 7: ‘first_match’, ‘if … else’, ‘iff’, ‘implies’

Lecture 8: first_match : further nuances

Chapter 6: System Functions and Tasks

Lecture 1: $onehot, $onehot0, $isunknown, $countones and assertion execution control tasks

Chapter 7: Multiply clocked properties and sequences

Lecture 1: Multiply clocked properties and sequences and operators 'and', 'or', etc.

Lecture 2: Multiple Clocks : Further nuances

Chapter 8: Local Variables and Endpoint sequence methods

Lecture 1: Local Variables

Lecture 2: Taking care of False Positive using Local Variables

Lecture 3: Modeling variable delay using local variables

Lecture 4: Local variable usage with 'and' and 'or' of sequences

Lecture 5: .triggered, .matched, Calling subroutines, sequence as a formal argument, sequen

Chapter 9: Misc IMPORTANT Topics

Lecture 1: ‘expect’, ‘assume’ Blocking ‘action block’

Lecture 2: Asynchronous FIFO Assertions

Lecture 3: Calling subroutines, sequence in sensitivity list and cyclic dependency

Lecture 4: Recursive Property

Lecture 5: Concurrent assertions fired from a procedural block and multiple implications

Chapter 10: IEEE-1800: LRM 2009/2012 features

Lecture 1: ‘let’ declarations and ‘checker’

Lecture 2: Checker : Legal and Illegal Conditions

Lecture 3: Strong/weak properties, 'always', 'eventually' and 'followed-by' operators

Chapter 11: QUIZZES

Lecture 1: QUIZ 1: Synchronous FIFO assertions

Lecture 2: QUIZ 2: Up-Down Counter

Lecture 3: QUIZ 3: Generic Bus Protocol

Lecture 4: QUIZ 4: PCI Bus Protocol

Chapter 12: SystemVerilog Functional Coverage Introduction and Methodology

Lecture 1: Introduction

Lecture 2: SystemVerilog Functional Coverage Methodology

Chapter 13: SystemVerilog Functional Coverage Language Features

Lecture 1: 'COVERGROUP' and 'COVERPOINT'

Lecture 2: 'bins'

Lecture 3: 'cross' coverage

Lecture 4: 'cross' further nuances

Lecture 5: 'transition' coverage

Lecture 6: widlcard bins, illegal_bins, ignore_bins, binsof, intersect

Lecture 7: 'bins' filtering

Lecture 8: 'Class' based functional coverage

Chapter 14: QUIZ :: Functional Coverage

Lecture 1: QUIZ :: Functional Coverage

Chapter 15: Performance implications and coverage methodology

Lecture 1: Performance implications and coverage methodology

Lecture 2: Querying for coverage

Lecture 3: coverage options and examples