FPGA Embedded Design, Part 4 – Microprocessor Design

Course Curriculum

Chapter 1: Introduction

Lecture 1: Introduction

Lecture 2: Instructor Introduction

Lecture 3: Motivation 1

Lecture 4: Motivation 2

Lecture 5: Motivation 3

Chapter 2: A Crash Course on Computer Architecture

Lecture 1: Parts of a Microprocessor-Based System

Lecture 2: Why we need a Bus Architecture

Lecture 3: The Bus Architecture

Lecture 4: The Data Bus

Lecture 5: The Address Bus

Lecture 6: The Control Bus

Lecture 7: How is it possible to drive a bus?

Lecture 8: The Memory Subsystem

Lecture 9: The Input/Output Subsystem

Chapter 3: Inside the CPU

Lecture 1: Parts of a CPU

Lecture 2: Arithmetic Logic Unit

Lecture 3: Registers

Lecture 4: Special Registers

Lecture 5: The Data Path

Lecture 6: Control Logic

Lecture 7: Instruction Encoding

Lecture 8: Instruction Execution

Chapter 4: Some Design Approaches

Lecture 1: CPU Design Criteria

Lecture 2: Structural vs. Behavioral Approaches

Lecture 3: Instruction Set Architecture

Lecture 4: Addressing Modes

Lecture 5: Some Addressing Mode Examples

Lecture 6: Number of Operands per Instruction

Lecture 7: CISC vs RISC Architectures

Lecture 8: Harvard vs. Von Neumann

Chapter 5: Let's Design a CPU!

Lecture 1: A Quick and Dirty Approach

Lecture 2: Program 1: Add Two Numbers

Lecture 3: Program 2: Fibonacci Sequence

Lecture 4: Program 3: Calculate a Factorial

Lecture 5: The Instructions we Need

Lecture 6: Your Personal Preferences

Lecture 7: Really, make your own choices!

Lecture 8: How many operands per instruction?

Lecture 9: CISC or RISC?

Lecture 10: Harvard or Von Neumann?

Lecture 11: System Design

Lecture 12: CPU Registers

Lecture 13: Memory Model

Lecture 14: Input/Output Model

Chapter 6: Instruction Set Design

Lecture 1: Instruction Set Design

Lecture 2: Instruction Encoding Spreadsheet

Lecture 3: Instruction Set Encoding

Lecture 4: Assembly Code for Program Example #1 (Adding Two Numbers)

Lecture 5: Assembly Code for Program Example #2 (Fibonacci Number)

Lecture 6: Assembly Code for Program Example #3 (Factorial)

Lecture 7: A Review of Addressing Modes

Lecture 8: A Review of Used Instructions

Lecture 9: Room for Growth

Chapter 7: Writing Our Own CPU RTL Code

Lecture 1: Writing your CPU RTL Code

Lecture 2: A bit of RTL and lots of Behavioral Code

Lecture 3: Registers

Lecture 4: State Machine Design

Lecture 5: Vivado Code

Lecture 6: The states of Jimmy

Lecture 7: The Opcodes

Lecture 8: Extracting the Opcode from the Instruction

Lecture 9: The Fetch Cycle

Chapter 8: Instruction Set Implementation

Lecture 1: Instruction Set Implementation

Lecture 2: Implementing the Instructions

Lecture 3: Addition

Lecture 4: Multiplication

Lecture 5: Update on MUL

Lecture 6: Register Transfer

Lecture 7: No Operation

Lecture 8: Load Immediate

Lecture 9: Compare Immediate

Lecture 10: Decrement

Lecture 11: Port Input

Lecture 12: Port Output

Lecture 13: Unconditional Branching

Lecture 14: Branch if Higher

Lecture 15: Branch on Equal

Chapter 9: System Design

Lecture 1: System Design

Lecture 2: Finishing up the System

Lecture 3: Coding in our own Machine Language

Lecture 4: Writing the Program Memory RTL

Lecture 5: Writing the Example Program #1 in our Memory

Lecture 6: Writing the Example Program #2 in our Memory

Lecture 7: Writing the Example Program #3 in our Memory

Chapter 10: Synthesis and Simulation

Lecture 1: A word on Synthesis

Lecture 2: Simulated Hardware for Program #1

Lecture 3: Simulated Hardware for Programs #2 and #3

Lecture 4: Vivado Simulation for Program #1

Lecture 5: Vivado Simulation for Program #2

Lecture 6: Vivado Simulation for Program #3