Introduction to RISC-V Interrupts

Introduction to RISC-V Interrupts, available at $54.99, has an average rating of 4, with 15 lectures, 1 quizzes, based on 1 reviews, and has 8 subscribers.

You will learn about Understand privilege levels, traps and control and status registers in RISC-V Platform Level Interrupt Controller Specification for RISC-V Sample implementation of PLIC module on RISC-V based FE310 SoC Writing assembly code, compiling, linking with GNU tools and debugging with OpenOCD and GDB Demonstration of interrupt generation & handling in RISC-V assembly This course is ideal for individuals who are Anyone interested in understanding the Platform Level Interrupt Controller Standard in RISC-V It is particularly useful for Anyone interested in understanding the Platform Level Interrupt Controller Standard in RISC-V.

Enroll now: Introduction to RISC-V Interrupts

Summary

Title: Introduction to RISC-V Interrupts

Price: $54.99

Average Rating: 4

Number of Lectures: 15

Number of Quizzes: 1

Number of Published Lectures: 15

Number of Published Quizzes: 1

Number of Curriculum Items: 16

Number of Published Curriculum Objects: 16

Original Price: $54.99

Quality Status: approved

Status: Live

What You Will Learn

Understand privilege levels, traps and control and status registers in RISC-V
Platform Level Interrupt Controller Specification for RISC-V
Sample implementation of PLIC module on RISC-V based FE310 SoC
Writing assembly code, compiling, linking with GNU tools and debugging with OpenOCD and GDB
Demonstration of interrupt generation & handling in RISC-V assembly

Who Should Attend

Anyone interested in understanding the Platform Level Interrupt Controller Standard in RISC-V

Target Audiences

Anyone interested in understanding the Platform Level Interrupt Controller Standard in RISC-V

Interrupts in RISC-V are governed by standards and specification. Each RISC-V core’s interrupt generation and handling process should be compliant to the specification.

This course discusses the following:

a. Privilege Levels in RISC-V

b. Traps in RISC-V

c. Platform Level Interrupt Controller (PLIC) Specification

d. Compares PLIC Implementation on FE310 SoC to Spec

e. Control and Status Registers (CSRs)

f. Instructions to read and write CSRs in RISC-V

g. Configuring GPIO peripheral in FE310 SoC

h. Configuring PLIC to allow GPIO interrupt

i. Configure MIE & MSTATUS CSRs on the core to enable machine mode interrupts and machine mode external interrupts

j. Installation of GNU tools (compilers, OpenOCD)

k. Test application in assembly to blink blue LED on Hifive1-Rev B board.

Students who enrol would be taken through a journey starting from basics of what are interrupts, exceptions and traps in RISC-V, followed by PLIC standard discussing the parameters, how to configure those parameters on PLIC to generate interrupt and claiming and completing the interrupt handling process and finally on writing an test application to blink LED.

The major exercise and focus on this course is on writing RISC-V assembly code, assembling & linking with GNU tools, generating ELF, and programming it on Hifive1-RevB board to blink blue LED on board.

Course Curriculum

Chapter 1: Introduction

Lecture 1: Course Overview

Chapter 2: Privilege Levels and Traps in RISC-V

Lecture 1: Privilege Levels in RISC-V

Lecture 2: Traps in RISC-V

Chapter 3: Platform Level Interrupt Controller Specification

Lecture 1: Need for PLIC Specification

Lecture 2: Interrupt Flow in PLIC

Lecture 3: Operational Block Diagram

Lecture 4: PLIC Parameters Memory Map In FE310 SoC

Chapter 4: Install tools, write simple assembly code, compile, link and generate ELF

Lecture 1: Install OpenOCD and GNU Toolchain

Lecture 2: Demo Compile, Load, Execute and Debug with OpenOCD and GDB

Chapter 5: Section 5: Control and Status Registers

Lecture 1: Introduction to & demonstration of accessing Control and Status Registers

Chapter 6: Hands on with Hifive1-Rev Board

Lecture 1: Introduction

Lecture 2: Configure GPIO 21

Lecture 3: Configure PLIC to allow GPIO 21 interrupt

Lecture 4: Configure E31 core CSRs to enable machine and machine external interrupt

Lecture 5: Test application to blink the blue LED and generate interrupt

Instructors

Benix Samuel Vincent Theogaraj
Embedded Solutions Provider & Contract Engineer

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