VSD – Timing ECO (engineering change order) webinar

VSD – Timing ECO (engineering change order) webinar, available at $44.99, has an average rating of 4.5, with 13 lectures, based on 179 reviews, and has 1027 subscribers.

You will learn about Design better chips Analyze designs, from power, performance and area perspective, altogether This course is ideal for individuals who are Anyone who wants to understand timing ECO strategies and how it impacts overall chip PPA (power, performance, area) or Anyone who wants to be called as "Signoff Timing Expert", rather than, "Signoff Timing Engineer" It is particularly useful for Anyone who wants to understand timing ECO strategies and how it impacts overall chip PPA (power, performance, area) or Anyone who wants to be called as "Signoff Timing Expert", rather than, "Signoff Timing Engineer".

Enroll now: VSD – Timing ECO (engineering change order) webinar

Summary

Title: VSD – Timing ECO (engineering change order) webinar

Price: $44.99

Average Rating: 4.5

Number of Lectures: 13

Number of Published Lectures: 13

Number of Curriculum Items: 13

Number of Published Curriculum Objects: 13

Original Price: $84.99

Quality Status: approved

Status: Live

What You Will Learn

Design better chips
Analyze designs, from power, performance and area perspective, altogether

Who Should Attend

Anyone who wants to understand timing ECO strategies and how it impacts overall chip PPA (power, performance, area)
Anyone who wants to be called as "Signoff Timing Expert", rather than, "Signoff Timing Engineer"

Target Audiences

Anyone who wants to understand timing ECO strategies and how it impacts overall chip PPA (power, performance, area)
Anyone who wants to be called as "Signoff Timing Expert", rather than, "Signoff Timing Engineer"

First, let’s define better? Better in terms of Power. Performance and Area

Every VLSI engineer, an RTL architect, or Lead Synthesis Engineer, or Senior Physical Designer, or Director of Signoff timing analysis – practically everyone is doing timing ECO at every step of their flow. I, being a part of Signoff timing analysis and Physical Design world, am doing ECO almost every day, and so I understood that its more than adding buffer and up-sizing/downsizing cells.

All of the factors or ways shown in above image impacts either dynamic power or short-circuit power or leakage power. The question is, do you know why do we still do it? Do you know how can we still do with minimally impact on other parameters? Yes, No, Don’t Know….

It’s time to unveil more than 9 strategies to do timing ECO and below are few of them�

Routing congestion aware timing ECO
Path based analysis ECO for selected endpoints
Replicated modules based timing ECO
Legalized timing ECO
Margin based timing ECO

…..and many more…

See, I told you, timing ECO is more than just adding buffers and sizing cells…Do you want to know all the strategies?
Do you want to be a better timing engineer? Engineering includes tons of changes and modifications from inception to final product. Hence its called Engineering Change Order (ECO)

Welcome all of you to my “Timing ECO webinar”, which was conducted along with ~50people on 6th Jan, 2018. Join and re-live the webinar.�

Course Curriculum

Chapter 1: Introduction

Lecture 1: Introduction

Chapter 2: Power, performance and area

Lecture 1: Factors impacting dynamic and short-circuit power

Lecture 2: Factors impacting short-circuit and leakage power

Lecture 3: Impact of add_buffer and sizing on performance and area

Lecture 4: Impact of load and Vt swap on performance and area

Chapter 3: ECO Strategies – Margin based and slack based fixing for selective end points

Lecture 1: Margin based DRV and setup-hold fixing

Lecture 2: Selective end-point based fixing with margin and slack range

Lecture 3: Slack based and number of path based fixing

Chapter 4: PBA fixing and leakage ECO

Lecture 1: PBA (path-based analysis) based and reg2reg based fixing

Lecture 2: Leakage recovery ECO strategy

Chapter 5: Hierarchical and Physical aware ECO

Lecture 1: Hierarchical ECO with top only hierarchical only and full chip ECO strategy

Lecture 2: Physical aware ECO

Chapter 6: Conclusion

Lecture 1: Bottle-neck analysis and conclusion

Instructors

Kunal Ghosh
Digital and Sign-off expert at VLSI System Design(VSD)

Rating Distribution

1 stars: 3 votes
2 stars: 2 votes
3 stars: 27 votes
4 stars: 71 votes
5 stars: 76 votes

Frequently Asked Questions

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