VSD – Physical Design Flow

Course Curriculum

Chapter 1: Physical Design Flow Overview

Lecture 1: Floor-Planning Steps

Lecture 2: Netlist Binding And Placement Optimization

Lecture 3: Placement Timing And Clock Tree Synthesis

Lecture 4: Clock Net Shielding

Lecture 5: Route – DRC Clean – Parasitics Extraction – Final STA

Chapter 2: Floorplanning

Lecture 1: Utilization Factor And Aspect Ratio

Lecture 2: Concept Of Pre-Placed Cells

Lecture 3: De-coupling Capacitors

Lecture 4: Power Planning

Lecture 5: Pin Placement And Logical Cell Placement Blockage

Chapter 3: Placement

Lecture 1: Net-list Binding And Placement

Lecture 2: Optimize Placement Using Estimated Wire Length And Capacitance

Lecture 3: Optimize Placement Conitnued

Chapter 4: Timing Analysis With Ideal Clocks

Lecture 1: Setup Timing Analysis And Introduction to Flip-Flop Setup Time

Lecture 2: Introduction To Clock Jitter and Uncertainty

Lecture 3: Setup Timing Analysis with Multiple Clocks

Lecture 4: Multiple Clock Timing Analysis And Introduction To Data Slew Check

Lecture 5: Data Slew Check

Chapter 5: Clock Tree Synthesis And Signal Integrity

Lecture 1: Clock Tree Routing And Buffering using H-Tree Algorithm

Lecture 2: Crosstalk And Clock Net Shielding

Lecture 3: Static Timing Analysis With Real Clocks

Lecture 4: Hold Timing Analysis Concluded

Lecture 5: Multiple Clocks Setup Timing Analysis With Real Clocks

Chapter 6: Routing And Design Rule Check (DRC)

Lecture 1: Introduction to Maze Routing – Lee's Algorithm

Lecture 2: Lee's Algorithm Conclusion

Lecture 3: Design Rule Check

Chapter 7: Parasitics Extraction

Lecture 1: Introduction to IEEE 1481 – 1999 SPEF format

Lecture 2: SPEF Representation of a NET

Lecture 3: Distributed Resistance And Capacitance Representation in SPEF

Lecture 4: SPEF Header Description, Physical Design Flow Conclusion and What Next !!

Chapter 8: Bonus – Technological advances happening in the world of opensource

Lecture 1: Next Generation Education Technology for VLSI Design Flow