Clock Domain Crossing Design & Verification (CDC)
Clock Domain Crossing Design & Verification (CDC), available at $199.99, has an average rating of 4, with 16 lectures, based on 4 reviews, and has 16 subscribers.
You will learn about The course covers all the basic concepts in clock domain crossings (CDC) analysis Understand how to avoid metastability in presence of Asynchronous clocks Understand how avoid correlation loss across synchronizers Understand design of FIFOs This course is ideal for individuals who are VLSI Designers It is particularly useful for VLSI Designers.
Enroll now: Clock Domain Crossing Design & Verification (CDC)
Summary
Title: Clock Domain Crossing Design & Verification (CDC)
Price: $199.99
Average Rating: 4
Number of Lectures: 16
Number of Published Lectures: 16
Number of Curriculum Items: 16
Number of Published Curriculum Objects: 16
Original Price: $199.99
Quality Status: approved
Status: Live
What You Will Learn
- The course covers all the basic concepts in clock domain crossings (CDC) analysis
- Understand how to avoid metastability in presence of Asynchronous clocks
- Understand how avoid correlation loss across synchronizers
- Understand design of FIFOs
Who Should Attend
- VLSI Designers
Target Audiences
- VLSI Designers
Learn Clock Domain Crossing (CDC) design and verification concepts deeply by vlsideepdive.
We are on a mission to inspire and develop people to achieve their goals in professional life. We enable people to learn deeply through bite-sized, interactive learning experiences. Our courses are structured and designed by leading experts in their respective fields.
Industry Expert: Vikas Sachdeva (Vikas Sachdeva is a semiconductor design professional with more than 17 years of experience in the VLSI Industry. Vikas manages everything related to CDC products at Real Intent. He has multiple published papers and 2 patents in CDC. )
The course covers the following topics in CDC
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Synchronous and Asynchronous Clocks
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Metastability
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Synchronizers
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MTBF
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Effects of Metastability
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Glitch on Synchronizers
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Pulse Width on Synchronizers
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Open and Closed Loop synchronizers
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Passing multiple signals across clock domains
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Counters
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Data path synchronization
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FIFOs
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Reset Paths
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CDC Verifications steps
Learn deeply
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For any experience level– Get started as a beginner with the fundamentals, or deep-dive right into advanced concepts. We have courses for ambitious people of all experience levels.
Master essential concepts – Build confidence with hands-on learning. You will get to see concepts visually, interact with the key ideas and solve challenging problems that get you to really think and learn deeply.
Stress less, learn better – Enjoy fun storytelling, guided problem solving, here your natural curiosity will automatically drive you.
Course Curriculum
Chapter 1: Introduction
Lecture 1: Introduction
Chapter 2: Synchronous and Asynchronous Clocks
Lecture 1: Synchronous and Asynchronous Clocks
Chapter 3: Metastability
Lecture 1: Metastability
Chapter 4: Synchronizers
Lecture 1: Synchronizers
Chapter 5: MTBF
Lecture 1: MTBF
Chapter 6: Synchronizer Deepdive
Lecture 1: Synchronizer Deepdive
Chapter 7: Effects of Metastabilty
Lecture 1: Effects of Metastabilty
Chapter 8: Glitch on synchronizers
Lecture 1: Glitch on synchronizers
Chapter 9: Pulse width on synchronizers
Lecture 1: Pulse width on synchronizers
Chapter 10: Open and closed loop synchronizers
Lecture 1: Open and closed loop synchronizers
Chapter 11: Passing multiple signals between asynchronous clock domains
Lecture 1: Passing multiple signals between asynchronous clock domains
Chapter 12: Synchronizer counters
Lecture 1: Synchronizer counters
Chapter 13: Datapath synchronization
Lecture 1: Datapath synchronization
Chapter 14: FIFOs
Lecture 1: FIFOs
Chapter 15: Reset paths
Lecture 1: Reset paths
Chapter 16: CDC Verification
Lecture 1: CDC Verification
Instructors
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Vikas Sachdeva
Trainer at vlsideepdive
Rating Distribution
- 1 stars: 0 votes
- 2 stars: 0 votes
- 3 stars: 2 votes
- 4 stars: 1 votes
- 5 stars: 1 votes
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