Embedded System Design with Xilinx Zynq FPGA and VIVADO

Course Curriculum

Chapter 1: Section_1_Overview with Xilinx VIVADO Design Suit and Zynq FPGA

Lecture 1: Overview of VIVADO and Zynq

Lecture 2: Section_1 Part 2 Overview of VIVADO and Zynq FPGA: Zynq Architecture Overview

Lecture 3: How to install VIVADO and Get 30 Day Evaluation License

Lecture 4: Section 1 How to Add Boards on VIVADO (Adding Zybo Board)

Lecture 5: Verilog Reference Guide From Digitronix Nepal

Lecture 6: VHDL Reference Guide From Digitronix Nepal

Lecture 7: Lab 1a-Basic Hardware Design with VIVADO IP Integrator for Zedboard

Lecture 8: Section 1 Lab 1a Output_Basic HDL implementation on ZedBoard FPGA

Lecture 9: Section 1 Lab 1b Basic HDL Design/Implement on Zybo FPGA

Lecture 10: Section 1 AXI Protocol Overview

Chapter 2: Section_2_Basic Embedded System Architecture and Designing with Zynq PS and GPIO

Lecture 1: Embedded System Overview & Lab 21 Memory Test Application on Zynq PS

Lecture 2: Hello World with Zynq FPGA

Lecture 3: Lab 21b Memory Test Application Zybo FPGA Implementation

Lecture 4: Lab22 Interfacing the Zynq PS and AXI GPIO IP (Buttons and Switch)

Chapter 3: Section_3_How to Create a Cusom IP (Led Controller) with VHDL in VIVADO for Zynq

Lecture 1: How to Create a Cusom LED Controller IP with VHDL in VIVADO for Zynq : Overview

Lecture 2: Section 3 Lab 1 Creating Custom IP :Create Led_controller IP in VHDL

Chapter 4: Section_4_Software Development with Xilinx SDK for Embedded Application

Lecture 1: Section 4_1 Lecture 1 and 2: Overview and Introduction to SDK

Lecture 2: Section_4_2 Lab: Writing Software Application for Led Controller IP

Lecture 3: Section 4_2 Demo of Lab: Implementing Led_controller on ZedBoard with SDK

Lecture 4: [Optional LAB] LED Controller in Verilog with VIVADO, ZedBoard & Ubuntu

Chapter 5: Section_5_Software Writing for Timer and Debugging with SDK

Lecture 1: Timer, Programming and Debugging Methodology with SDK on Zynq FPGA

Lecture 2: Lab 5-Software Writing for Timer and Debugging Using Software Development

Chapter 6: Section_6_Configuration and Bootloading with SDK (Creating Custom Bootable File)

Lecture 1: Overview of Configuration and Bootloading with SDK

Lecture 2: Lab 6 Creating Bootable file of the application project for SD

Lecture 3: Lab 62- Creating Bootable File for Zynq FPGA

Chapter 7: Section_7_Embedded Design with VIVADO High Level Synthesis-HLS: Counter Design

Lecture 1: Section 7 VIVADO HLS Design Methodology & Lab 71: Counter Design with HLS

Chapter 8: Section_8_VIVADO Tcl Scripting: Creating VIVADO Project with Tcl Commands

Lecture 1: Section 8 VIVADO Tcl Scripting

Lecture 2: Section 8 Lab 81 Creating Basic Project (Half Adder) with Tcl Commands in VIVADO

Lecture 3: Section 8 Lab82 importing Tcl scripts form Github/Tcl file(Creating BCD Counter)

Lecture 4: Tcl Reference Guide From Digitronix Nepal

Chapter 9: Section_9_ Debugging with VIVADO: Hardware and Software Debuggin

Lecture 1: Section 91 Debugging with VIVADO Hardware and Software Debugging

Lecture 2: Lab91: GPIO Base Design for Debugging

Lecture 3: Lab92: Debugging with ILA on Lab91

Lecture 4: Lab93: Debugging with VIO on Lab92

Lecture 5: Lab 94: XADC Debugging Demo with VIVADO and Zybo FPGA

Chapter 10: Section_10 Vitis/VIVADO 2020.1 Project Session

Lecture 1: Creating Basic GPIO project with Vitis 2020.1

Chapter 11: VIVADO 2021.1 Session for VDMA IP Pipeline Design for PYNQ

Lecture 1: VDMA-Video Pipeline Design for PYNQ Board on VIVADO 2021.1

Chapter 12: Petalinux Development with Zynq

Lecture 1: Developing Petalinux for Custom VIVADO Project [Led Controller Project]

Chapter 13: Conclusion & Bonus Lecture

Lecture 1: What Next?

Lecture 2: Books and Reference Links