VHDL Circuit Design and FPGAs with VIVADO and MODELSIM

Course Curriculum

Chapter 1: Introduction

Lecture 1: Outline

Chapter 2: Entity, Architecture and VHDL Operators

Lecture 1: ENTITY in VHDL

Lecture 2: ARCHITECTURE in VHDL

Lecture 3: Data Objects in VHDL

Lecture 4: VIVADO Application: Creating I/O Ports for Different Data Types and Port Pin Num

Lecture 5: Data types

Lecture 6: VIVADO Application: Negative Numbers in VHDL, Positive and Natural Numbers

Lecture 7: VHDL Operators, assignment operators, logical ops, logical and arithmetic ops

Lecture 8: VIVADO Application: Shift operators and abs() function simulation in VIVADO

Lecture 9: VHDL Operators, rem, mod, rem, abs, &, **

Lecture 10: Generic Statement

Lecture 11: VIVADO Application: Power operator **, rem() and mod() simulation in VIVADO

Chapter 3: Combinational Circuit Design in VHDL

Lecture 1: When and With-Select Statements

Lecture 2: VHDL Generate Statement

Lecture 3: VIVADO Application: Generate Statement, MUX 2×1 and When-Else statement

Lecture 4: MUXES in VHDL, Part-1

Lecture 5: MUXES in VHDL, Part-2

Lecture 6: VIVADO Application: IO Planning Using Vivado

Lecture 7: MUXES in VHDL, Part-3

Lecture 8: Binary Encoders in VHDL

Lecture 9: BCD Encoder and BCD to SS Display Converter in VHDL

Chapter 4: Simulation of VHDL Programs, and Testbench Writing

Lecture 1: Testbench writing for the simulation of VHDL programs

Lecture 2: Example for testbench writing

Lecture 3: VIVADO Application: Writing TEST-BENCH and VIVADO Simulation Using TEST-BENCH

Chapter 5: Simulation Using MODELSIM

Lecture 1: Simulation using modelsim, a basic example

Lecture 2: ModelSim Simulation of VHDL Codes with TestBenches

Lecture 3: Displaying Signal Values Using Modelsim

Lecture 4: Simulating VHDL Codes With Modelsim Without Using TestBenches

Chapter 6: User Defined Data Types, Constrained and Unconstrained Arrays, Matrices in VHDL

Lecture 1: User defined data types and contrained arrays in VHDL

Lecture 2: Unconstrained arrays and port arrays

Lecture 3: Matrices and 3D arrays in VHDL

Lecture 4: MODELSIM Simulation for user-defined data type attributes

Chapter 7: Sequential circuits, process, clock divider, sample seq. circ. implementations

Lecture 1: Process, if-then-else, D-flip flop in VHDL are explained

Lecture 2: JK Flip-Flop, T Flip-Flop, Counter and MUX implementation in VHDL using Process

Lecture 3: Clock divider digital circuits

Lecture 4: Clock divider (frequency divider) implementation in VHDL

Lecture 5: SS Display Driver Implementation in VHDL

Lecture 6: VIVADO Application: Parallel Operation, Signal Objects vs Variable Objects

Lecture 7: MODELSIM Simulation of T type Flip-Flop

Lecture 8: MODELSIM Simulation: Signal Object Update is NOT Immediate

Lecture 9: MODELSIM Simulation: Signal Object Behavior-2

Lecture 10: MODELSIM Simulation: Clock Division in VHDL, Part-1

Lecture 11: MODELSIM Simulation: Clock Division in VHDL, Part-1

Chapter 8: VHDL Statements, Wait, Wait On, Wait Until, Wait For and CASE

Lecture 1: VHDL Statements, Wait, Wait On, Wait Until and Wait For

Lecture 2: Case Statement

Chapter 9: Loops in VHDL

Lecture 1: Loops in VHDL

Lecture 2: Loop Simulation Using MODELSIM

Chapter 10: Packages, Components, Functions, Procedures

Lecture 1: Packages in VHDL

Lecture 2: VIVADO Application: Package declaration and Its use in the main program.

Lecture 3: Components in VHDL

Lecture 4: VIVADO Application: Defining components and using them in VHDL codes

Chapter 11: Intellectual Property (IP) Cores, and Use of IP Cores for VHDL Design

Lecture 1: VIVADO Application: Add/Subtract IP Code use in VHDL Code

Chapter 12: Programming FPGA Using ARTY-7 35T Evaluation Board, Boolean Board and Vivado

Lecture 1: Constraints Files Used For the Programming of FPGAs

Lecture 2: Programming FPGA Using ARTY-7 35T Evaluation Board and XILINX VIVADO

Lecture 3: Programming Boolean Board to Display Digits 0-9 on SSD

Chapter 13: Fixed and Floating Point Numbers in VHDL

Lecture 1: Simulation of Fixed-Point VHDL Implementations in VIVADO