VSD – Clock Tree Synthesis – Part 2
VSD – Clock Tree Synthesis – Part 2, available at $54.99, has an average rating of 4.5, with 25 lectures, based on 483 reviews, and has 2864 subscribers.
You will learn about CTS Quality Checks (Skew, Power, Latency, etc.) H-Tree Quality Check of H-Tree Clock Tree Buffering Buffered H-Tree H-Tree with uneven spread of Flops Advanced H-Tree for Million Flops Power Aware CTS (clock gating) Static Timing Analysis with Clock Tree This course is ideal for individuals who are Individuals keen to learn about VLSI and Chip World It is particularly useful for Individuals keen to learn about VLSI and Chip World.
Enroll now: VSD – Clock Tree Synthesis – Part 2
Summary
Title: VSD – Clock Tree Synthesis – Part 2
Price: $54.99
Average Rating: 4.5
Number of Lectures: 25
Number of Published Lectures: 25
Number of Curriculum Items: 25
Number of Published Curriculum Objects: 25
Original Price: $84.99
Quality Status: approved
Status: Live
What You Will Learn
- CTS Quality Checks (Skew, Power, Latency, etc.)
- H-Tree
- Quality Check of H-Tree
- Clock Tree Buffering
- Buffered H-Tree
- H-Tree with uneven spread of Flops
- Advanced H-Tree for Million Flops
- Power Aware CTS (clock gating)
- Static Timing Analysis with Clock Tree
Who Should Attend
- Individuals keen to learn about VLSI and Chip World
Target Audiences
- Individuals keen to learn about VLSI and Chip World
This course is a follow-up course of “VLSI Academy – Clock tree synthesis – Part 1”. So its highly recommended to go through Part 1 of clock tree synthesis
Clock is a critical part of any VLSI chip, and this course takes you to the advanced level of building a clock tree from scratch for millions of flop.
While we plan to add some experimental videos and courses very soon, as a supplement, this one has real time examples and problems that you see on a real chip, and even solutions to those problems
The course is structured in below format:
1) Introduction
2) Clock tree optimization checklist
3) How to build clock tree for uneven spread of clock end-points
4) Power aware clock tree synthesis
5) Static timing analysis with real clocks
Sounds interesting !! Right !! So get in and have the greatest learning experience like you had never before
See you in class!!
Course Curriculum
Chapter 1: Introduction
Lecture 1: Introduction
Chapter 2: Clock Tree Optimization Checklist
Lecture 1: Optimization Checklist
Lecture 2: Leakage Current Reduction Technique
Lecture 3: Short Circuit Current Reduction Technique
Lecture 4: Clock Tree Optimized
Lecture 5: Optimized Clock Tree Power And Latency Check
Chapter 3: Uneven Spread of Clock Endpoints
Lecture 1: Clock Tree for Uneven Spread of Clock End Points
Lecture 2: Logical to Physical Connections
Lecture 3: Checklist
Lecture 4: Advanced H-Tree for Million Flop clock endpoints with uneven spread
Chapter 4: Power Aware Clock Tree Synthesis
Lecture 1: Introduction to clock gating cells
Lecture 2: Introduction to Delay Tables
Lecture 3: Delay Table Usage – I
Lecture 4: Delay Table Usage – II
Lecture 5: Clock Gating Technique using AND Gate and Skew Issue
Lecture 6: Solution to Skew Issue
Lecture 7: Clock Gating technique using both AND and OR gate
Lecture 8: Clock Gating Technique using universal NAND gate
Lecture 9: Clock Gating Technique on real Chip and its impact on Power
Chapter 5: Static Timing Analysis
Lecture 1: Setup Timing Analysis with Real Clocks
Lecture 2: Introduction to Data Arrival Time, Data Required Time and Slack
Lecture 3: Impact of unbalanced Skew on Setup Time
Lecture 4: Hold Timing Analysis with Real Clocks
Lecture 5: Impact of unbalanced Skew on Hold Time
Chapter 6: Summary
Lecture 1: Topics Learned and More to come!!
Instructors
-
Kunal Ghosh
Digital and Sign-off expert at VLSI System Design(VSD)
Rating Distribution
- 1 stars: 7 votes
- 2 stars: 15 votes
- 3 stars: 81 votes
- 4 stars: 197 votes
- 5 stars: 183 votes
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