VSD – Custom Layout

Course Curriculum

Chapter 1: Introduction

Lecture 1: Course content

Chapter 2: Inception of layout – CMOS fabrication process

Lecture 1: Create active regions

Lecture 2: Formation of N-well and P-well

Lecture 3: Formation of gate terminal

Lecture 4: Lightly doped drain (LDD) formation

Lecture 5: Source drain formation

Lecture 6: Local interconnect formation

Lecture 7: Higher level metal formation

Chapter 3: Introduction to ‘corner stitching’ and ‘tech files’

Lecture 1: INV.mag

Lecture 2: min2.tech

Lecture 3: Corner stitching introduction

Lecture 4: Corner stitch to planes to tiles

Lecture 5: Active tile types and tech file content

Lecture 6: Contacts and styles

Lecture 7: Connect section for circuit extraction

Chapter 4: Design rule checking (DRC)

Lecture 1: Introduction to DRC and lambda design rules

Lecture 2: Poly extension and poly to diffusion spacing rules

Lecture 3: Poly to diffusion spacing and diffusion contact width rules

Lecture 4: Metal1 width and poly to metal1 spacing rules

Lecture 5: Contact spacing and minimum active width rules

Lecture 6: From logic to layout to SPICE

Chapter 5: Introduction to euler's path and stick diagram

Lecture 1: Introduction to simple path, euler's path and euler's circuit

Lecture 2: Introduction to stick diagram

Lecture 3: Derive actual dimension from stick diagram

Chapter 6: Art of layout using Euler's path plus Stick diagram

Lecture 1: Pre-layout simulation

Lecture 2: Layout using 'only' stick diagram

Lecture 3: Euler's path for Fn – Input gate ordering

Lecture 4: Improved stick diagram for new gate input ordering

Lecture 5: Abstract layout from stick diagram

Lecture 6: Derive actual dimension for Fn

Lecture 7: Script to create layout

Lecture 8: draw_fn.tcl

Lecture 9: Final layout and input/output labelling

Chapter 7: Conclusion, acknowledgements and what next!!!

Lecture 1: fn_prelayout.cir

Lecture 2: fn_postlayout.mag

Lecture 3: Post-layout simulation and conclusion