VSD – Distributed timing analysis within 100 lines code
VSD – Distributed timing analysis within 100 lines code, available at $19.99, has an average rating of 4.5, with 15 lectures, based on 62 reviews, and has 3891 subscribers.
You will learn about Learn, code, analyze distributed framework Take up and run STA for challenging designs with hugh instance count and witness the benefits of distributed STA This course is ideal for individuals who are This course is for people who are proficient with timing concepts and want to move a level ahead, and stay ahead of curve or Anyone enthusiastic to learn about distributed timing analysis from scratch i.e. from C++ code level It is particularly useful for This course is for people who are proficient with timing concepts and want to move a level ahead, and stay ahead of curve or Anyone enthusiastic to learn about distributed timing analysis from scratch i.e. from C++ code level.
Enroll now: VSD – Distributed timing analysis within 100 lines code
Summary
Title: VSD – Distributed timing analysis within 100 lines code
Price: $19.99
Average Rating: 4.5
Number of Lectures: 15
Number of Published Lectures: 15
Number of Curriculum Items: 15
Number of Published Curriculum Objects: 15
Original Price: $84.99
Quality Status: approved
Status: Live
What You Will Learn
- Learn, code, analyze distributed framework
- Take up and run STA for challenging designs with hugh instance count and witness the benefits of distributed STA
Who Should Attend
- This course is for people who are proficient with timing concepts and want to move a level ahead, and stay ahead of curve
- Anyone enthusiastic to learn about distributed timing analysis from scratch i.e. from C++ code level
Target Audiences
- This course is for people who are proficient with timing concepts and want to move a level ahead, and stay ahead of curve
- Anyone enthusiastic to learn about distributed timing analysis from scratch i.e. from C++ code level
This webinar was conducted on 26th May 2018.
1) What happens when you type set_multi_cpu_usage -localCpu 4 on your EDA timing shell?
2) What happens when you type set_multi_cpu_usage -localCpu 4 -numThreads 4 on your EDA timing shell?
I had a curiosity, while working at my previous design companies, about how jobs are getting spawned on different machines? What if there are less machines and more jobs, and vice versa? How does the algorithm of a timing engine handles this?
I myself used to setup the entire distributed MMMC framework for timing tools at customer place, which was just setting the right variables (set_multi_cpu_usage), but never knew what goes behind the tools. Its the curiosity which leads to queries which leads to exploration and finally, leads to
answers. I found my answers from Tsung-Wei, who is the architect of popular opensource STA Tool Opentimer.
We all know timing analysis is a really important task in overall chip design flow and its so complex and difficult task. The chip that we incorporate today has billions of transistors, resulting timing analysis runtime is tool large. Also, we need to analyze timing under different conditions, so its not just a single run that you get a final result. While there are several solutions to mitigate this computation issue, the problem is most of the work is architecturally constrained by
single machine. And as design complexity continue to grow larger and larger, we have to add more and more CPU and memories to the machine, but not very cost-efficient
There are multiple places, we can introduce distributed computing to timing and major motivation is to speed up the timing closure. We have to analyze timing under different range of conditions, typically quantified as modes (test mode, functional mode) and corner (PVT). The number of combinations (timing views) you have to run is typically increasing exponentially with lower nodes. That’s where you need to need to distribute timing analyses across different machines.
So let’s distribute it and do it within 100lines of code using DTCraft – A High-performance cluster computing engine. Welcome to the webinar on “Distributed timing analysis within 100 lines of code”
Do you want to find your answers too? Enroll in the upcoming webinar on “Distributed timing analysis” with Tsung-Wei, do labs on your own,
understand the framework and I can guarantee you would be a better STA engineer or Lead than you were before
Speaker Profile:Tsung-Wei Huang
Tsung-Wei Huang is Research Assistant Professor, in Department of Electrical and Computer Engineering at University of Illinois at Urbana-Champaign, IL, USA. He has done his PhD in Electrical and Computer Engineering at UIUC. He holds 2 patents and more than 30 Conference and Journal Paper publications
Course Curriculum
Chapter 1: Introduction
Lecture 1: Introduction
Lecture 2: Need for distributed-STA
Chapter 2: Explain parallelism in right way
Lecture 1: DTCraft installation steps and webinar outline
Lecture 2: Distributed timing concept and big-data tool issues
Lecture 3: Hard-coded distributed MMMC framework
Lecture 4: A new solution – DTCraft
Chapter 3: DTCraft Labs
Lecture 1: Vanilla 'Hello World example using DTCraft
Lecture 2: 'hello world' example description
Lecture 3: Steps to compile 'hello world' example
Lecture 4: Steps to run 'hello_world' in DTCraft cluster
Chapter 4: DTCraft labs in static timing analysis
Lecture 1: Distributed timing analysis for 3 timing views on 3 machines
Lecture 2: DTCraft test-run with 3 tming views using 2 machines
Lecture 3: QnA with participants on DtCraft runs for 3-timing views
Lecture 4: Steps to overload memory and assignment description
Chapter 5: Conclusion
Lecture 1: Conclusion and acknowledgements
Instructors
-
Kunal Ghosh
Digital and Sign-off expert at VLSI System Design(VSD) -
Tsung-Wei Huang
Assistant Professor, University of Wisconsin at Madison
Rating Distribution
- 1 stars: 2 votes
- 2 stars: 4 votes
- 3 stars: 18 votes
- 4 stars: 22 votes
- 5 stars: 16 votes
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