VSD Intern – Mixed Signal Physical Design Flow with Sky130
VSD Intern – Mixed Signal Physical Design Flow with Sky130, available at $34.99, has an average rating of 4.05, with 19 lectures, based on 30 reviews, and has 258 subscribers.
You will learn about Multi-height RTL2GDS flow for Mixed Signal SoC Steps to convert basic analog block to hard-macro Steps to use hard-macro in OpenLANE RTL2GDS flow Labs to verify Macro based Physical Design flow This course is ideal for individuals who are Students looking for a platform to enter into Physical design world or Experts looking forward to explore Macro based OpenLANE flow It is particularly useful for Students looking for a platform to enter into Physical design world or Experts looking forward to explore Macro based OpenLANE flow.
Enroll now: VSD Intern – Mixed Signal Physical Design Flow with Sky130
Summary
Title: VSD Intern – Mixed Signal Physical Design Flow with Sky130
Price: $34.99
Average Rating: 4.05
Number of Lectures: 19
Number of Published Lectures: 19
Number of Curriculum Items: 19
Number of Published Curriculum Objects: 19
Original Price: $89.99
Quality Status: approved
Status: Live
What You Will Learn
- Multi-height RTL2GDS flow for Mixed Signal SoC
- Steps to convert basic analog block to hard-macro
- Steps to use hard-macro in OpenLANE RTL2GDS flow
- Labs to verify Macro based Physical Design flow
Who Should Attend
- Students looking for a platform to enter into Physical design world
- Experts looking forward to explore Macro based OpenLANE flow
Target Audiences
- Students looking for a platform to enter into Physical design world
- Experts looking forward to explore Macro based OpenLANE flow
This course describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, OpenLANE. It also discusses the steps to modify the current IP layouts in order to ensure its acceptance by the EDA tools
Mixed signal SoC is a chip which contains both analog and digital blocks. The designers are adding more analog circuitry and increasing their complexities day by day. Not only that, they also contain digital control logic. As the process nodes shrink, the demand for integration grows. A divide and conquer approach is followed, where the analog and digital structures were dealt with separately. Usually, an analog IP (Intellectual Property) is bought as black- box
To implement a RTL-to-GDS flow for mixed signal SoC, there is need to establish communication between the analog and digital blocks. For this integration to happen, hierarchical level of abstraction with either analog or digital as top level is required. In order to carry out this task, OpenROAD project can be utilized
Hope you enjoy the session. Any constructive feedback is appreciated
Future Work
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To include custom LIB for macro and include timing constraints.
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To perform PNR on macro of triple-height or more
Acknowledgement
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Kunal Ghosh, Co-founder, VSD Corp. Pvt. Ltd
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Openlane team, Efabless corporation
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Tim Edwards, Senior Vice President of Analog and Design at efabless corporation
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Nickson Jose, VLSI Engineer
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Prithivi Raj K, National Institute of Technology Tiruchirapalli
Course Curriculum
Chapter 1: Generating hard-macro LEF for basic analog block
Lecture 1: Introduction to mixed-signal flow and EDA tools used
Lecture 2: Macro LEF file modification
Lecture 3: Steps to create pins in macro LEF
Lecture 4: Steps to modify LEF class, origin and site properties
Lecture 5: Steps to modify LEF bounding box property
Lecture 6: Steps to modify LEF port property
Lecture 7: LEF file modifications summary
Chapter 2: Macro based RTL2GDS using OpenLANE/Sky130
Lecture 1: Steps to setup new OpenLANE project
Lecture 2: Steps to setup input files in OpenLANE project
Lecture 3: Steps to setup macro LEF files for OpenLANE flow
Lecture 4: Final OpenLANE config file settings
Lecture 5: Prep design and add LEFs in OpenLANE flow
Chapter 3: RTL2GDS Physical Design flow steps
Lecture 1: Short theory on RTL2GDS flow
Lecture 2: RTL synthesis and floorplan step
Lecture 3: Global and detailed placement
Lecture 4: Tap-Decap detailed placement
Lecture 5: PDN generation
Lecture 6: Final routing and GDS generation
Lecture 7: Final layout review and conclusion
Instructors
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Kunal Ghosh
Digital and Sign-off expert at VLSI System Design(VSD) -
Praharsha Mahurkar
Happy Learning
Rating Distribution
- 1 stars: 2 votes
- 2 stars: 1 votes
- 3 stars: 8 votes
- 4 stars: 4 votes
- 5 stars: 15 votes
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