VSD – Library characterization and modelling – Part 1
VSD – Library characterization and modelling – Part 1, available at $39.99, has an average rating of 4.3, with 39 lectures, based on 375 reviews, and has 1886 subscribers.
You will learn about Understand timing, noise and power libraries syntax and semantics Develop models for logic gates and macros Use the above generated models and do STA This course is ideal for individuals who are Research professionals or Graduate students or Circuit and PDK designers or Characterization engineers or CAD developers or Managers, Mentors and the merely curious It is particularly useful for Research professionals or Graduate students or Circuit and PDK designers or Characterization engineers or CAD developers or Managers, Mentors and the merely curious.
Enroll now: VSD – Library characterization and modelling – Part 1
Summary
Title: VSD – Library characterization and modelling – Part 1
Price: $39.99
Average Rating: 4.3
Number of Lectures: 39
Number of Published Lectures: 39
Number of Curriculum Items: 39
Number of Published Curriculum Objects: 39
Original Price: $84.99
Quality Status: approved
Status: Live
What You Will Learn
- Understand timing, noise and power libraries syntax and semantics
- Develop models for logic gates and macros
- Use the above generated models and do STA
Who Should Attend
- Research professionals
- Graduate students
- Circuit and PDK designers
- Characterization engineers
- CAD developers
- Managers, Mentors and the merely curious
Target Audiences
- Research professionals
- Graduate students
- Circuit and PDK designers
- Characterization engineers
- CAD developers
- Managers, Mentors and the merely curious
If you are STA engineer or PNR engineer or CTS engineer or, in general, a physical designer or Synthesis engineer, you must have definitely come across the word ‘Library’. This course explains you, in detail, what it exactly means.
You can call Library as the soul and heart of Semiconductor industries. Without them, you can’t have single chip out. Without the knowledge of Libraries, all other courses are incomplete.
Guess what, you are at the right page. This course gives a comprehensive overview of characterization techniques and advanced modelling of circuits for modern and advanced nodes.
Not only that, you will see what goes behind designing a simple single input inverter. The gates like inverter, buffer, AND, OR are all called as cell, and you will be amazed to see how are the represented in real IC design.
This course is designed in collaboration with leading characterization company Paripath, who have designed the state-of-the-art characterization software called GUNA
I would like to Thank complete Paripath team for helping me in designing experiments for this course. This course is motivated by desire to fill gap on characterization and modelling
Trademark:
Liberty is a registered trademark of Synopsys Inc.
Verilog is a registered trademark of Cadence Design Systems, Inc.
SDF and SPEFare trademarks of Open Verilog International
Get in right now and have an unforgettable journey of your life…
Happy Learning!!
Course Curriculum
Chapter 1: Introduction
Lecture 1: Introduction and Acknowledgements
Lecture 2: Need for characterization
Chapter 2: Cell design and characterization flows
Lecture 1: Inputs for cell design flow
Lecture 2: Circuit design step
Lecture 3: Layout design step
Lecture 4: Typical characterization flow
Chapter 3: General Timing characterization parameters
Lecture 1: Timing threshold definitions
Lecture 2: Propagation delay and transition time
Lecture 3: Output current model and CCS table
Lecture 4: Output voltage waveform and introduction to tristate buffer
Lecture 5: Different transitions for tristate buffer
Chapter 4: Timing characterization parameters for registers
Lecture 1: Netlist connectivity for latch and flipflop
Lecture 2: Library setup time as a function of data and clock transition time
Lecture 3: True single phase clocked (TSPC) register for hold time evaluation
Lecture 4: Library setup time for TSPC register
Lecture 5: Hold time, recovery & removal time evaluation
Chapter 5: Noise characterization and modelling
Lecture 1: Introduction to noise – Crosstalk glitch and delta delay
Lecture 2: Introduction to channel connected components (CCC)
Lecture 3: ccsn_first_stage, ccsn_last_stage and VIVO model based dc_current
Lecture 4: Need of dc_current attribute
Lecture 5: Noise immunity curve, propagated_noise_high and propagated_noise_low
Lecture 6: stage_type attribute and need for tie_hi cells
Lecture 7: Miller cap, arc based ccs noise model and full noise library
Chapter 6: Power characterization and modelling
Lecture 1: Static power – Subthreshold current and junction leakage current
Lecture 2: Static power – Tunnelling current
Lecture 3: Internal leakage power – leakage_current and leakage_power groups
Lecture 4: Internal leakage power – cell_leakage_power & Tunneling curent – gate_leakage
Lecture 5: Dynamic power – Switching current
Lecture 6: Dynamic power – Short-circuit current
Lecture 7: Switching power and short-circuit power modelling
Lecture 8: Hidden power concept and modelling
Chapter 7: Timing modelling
Lecture 1: Groups and attributes
Lecture 2: Library group and its attributes
Lecture 3: Cell groups and combinational function pin groups
Lecture 4: Flip-flop modelling using 'ff' group
Lecture 5: Latch modelling using 'latch' group
Lecture 6: Introduction to 'statetable' and latch description using 'statetable' group
Lecture 7: Flip-flop modelling using 'statetable' group and introduction to 'driver model'
Chapter 8: Conclusion
Lecture 1: Driver model, receiver model and conclusion
Instructors
-
Kunal Ghosh
Digital and Sign-off expert at VLSI System Design(VSD)
Rating Distribution
- 1 stars: 11 votes
- 2 stars: 6 votes
- 3 stars: 57 votes
- 4 stars: 126 votes
- 5 stars: 175 votes
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