VSD – RTL Synthesis Q&A Webinar

VSD – RTL Synthesis Q&A Webinar, available at $29.99, has an average rating of 3.9, with 11 lectures, based on 18 reviews, and has 484 subscribers.

You will learn about Students will get structured answers to queries which they might otherwise find difficult to search online Perception about synthesis and opensource tools will change Students and professionals from other fields will be excited to choose Synthesis as their full-time career as so many things are yet to explore This course is ideal for individuals who are Anyone who wants to enter VLSI front-end design field should take this course, as this course will answer lot of questions related to synthesis in general or Anyone looking to start using opensource tool Yosys for synthesis or Anyone curious to know what's happening in the world of RTL synthesis It is particularly useful for Anyone who wants to enter VLSI front-end design field should take this course, as this course will answer lot of questions related to synthesis in general or Anyone looking to start using opensource tool Yosys for synthesis or Anyone curious to know what's happening in the world of RTL synthesis.

Enroll now: VSD – RTL Synthesis Q&A Webinar

Summary

Title: VSD – RTL Synthesis Q&A Webinar

Price: $29.99

Average Rating: 3.9

Number of Lectures: 11

Number of Published Lectures: 11

Number of Curriculum Items: 11

Number of Published Curriculum Objects: 11

Original Price: $189.99

Quality Status: approved

Status: Live

What You Will Learn

Students will get structured answers to queries which they might otherwise find difficult to search online
Perception about synthesis and opensource tools will change
Students and professionals from other fields will be excited to choose Synthesis as their full-time career as so many things are yet to explore

Who Should Attend

Anyone who wants to enter VLSI front-end design field should take this course, as this course will answer lot of questions related to synthesis in general
Anyone looking to start using opensource tool Yosys for synthesis
Anyone curious to know what's happening in the world of RTL synthesis

Target Audiences

Anyone who wants to enter VLSI front-end design field should take this course, as this course will answer lot of questions related to synthesis in general
Anyone looking to start using opensource tool Yosys for synthesis
Anyone curious to know what's happening in the world of RTL synthesis

Welcome to first ever QnA webinar on RTL synthesis using Yosys. This webinar was conducted on 19th May, 2018 with Clifford Wolf

Its a Q&A webinar on RTL Synthesis, by Clifford Wolf. Clifford is architect of Yosys which is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.

Clifford
will be answering 23 queries on RTL synthesis. TOP23 query submissions are directly eligible for certificates from our company VSD Corp. Pvt. Ltd.

Note of Appreciation
I have worked with Clifford in my course on TCL programming Part 1
& 2, and really Thank him for all his guidance for making of TCL
programming course.

Clifford has more than 20+ years of experience and is been known the Architect and Father of Yosys, OpenSCAD (now maintained by Marius Kintel), SPL (a not very popular scripting language), EmbedVM (a very simple compiler+vm for 8 bit micros), Lib(X)SVF (a library to play SVF/XSVF files over JTAG), ROCK Linux (discontinued since 2010)

All the best and happy learning.

Course Curriculum

Chapter 1: Introduction

Lecture 1: Introduction

Lecture 2: Queries next stage RTL design, HDL and asynchronous logic synthesis answered

Lecture 3: Query on best way to do synthesis answered

Lecture 4: Queries on ideal clock, synthesis challenges across nodes and multiple clock

Lecture 5: Queries on synopsys lib file reading and synthesis constraints answered

Lecture 6: Queries on partitioning, power estimation and power efficient RTL answered

Lecture 7: Queries on testbench for maximum coverage and physical aware Yosys answered

Lecture 8: Yosys project start-up story answered

Lecture 9: Queries on machine learning in Yosys, handling scan logic and derates answered

Lecture 10: Queries on next milestones of Yosys and fsm_recode command answered

Lecture 11: Query on equivalence check and conclusion

Instructors

Kunal Ghosh
Digital and Sign-off expert at VLSI System Design(VSD)

Rating Distribution

1 stars: 1 votes
2 stars: 2 votes
3 stars: 4 votes
4 stars: 6 votes
5 stars: 5 votes

Frequently Asked Questions

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You can view and review the lecture materials indefinitely, like an on-demand channel.

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