VSD – Signal Integrity

VSD – Signal Integrity, available at $79.99, has an average rating of 4.13, with 42 lectures, 9 quizzes, based on 532 reviews, and has 2943 subscribers.

You will learn about To Learn Chip Design with minimal Crosstalk in the circuits. To Design a Chip with minimal errors. This course is ideal for individuals who are VLSI Engineers keen to Learn Backend of Chip Design or Physical Design Engineer or Students Learning VLSI Engineering It is particularly useful for VLSI Engineers keen to Learn Backend of Chip Design or Physical Design Engineer or Students Learning VLSI Engineering .

Enroll now: VSD – Signal Integrity

Summary

Title: VSD – Signal Integrity

Price: $79.99

Average Rating: 4.13

Number of Lectures: 42

Number of Quizzes: 9

Number of Published Lectures: 42

Number of Published Quizzes: 9

Number of Curriculum Items: 51

Number of Published Curriculum Objects: 51

Original Price: $84.99

Quality Status: approved

Status: Live

What You Will Learn

To Learn Chip Design with minimal Crosstalk in the circuits.
To Design a Chip with minimal errors.

Who Should Attend

VLSI Engineers keen to Learn Backend of Chip Design
Physical Design Engineer
Students Learning VLSI Engineering

Target Audiences

VLSI Engineers keen to Learn Backend of Chip Design
Physical Design Engineer
Students Learning VLSI Engineering

Performance, Power and Area are the three main pillars of the Chip Design, Crosstalk can hamper all three.�

Crosstalk is the interference caused due to communication between the circuits

Lets learn to ” HOW TO REDUCE CROSSTALK ? ” to achieve a efficient Chip design which give the best performance, uses optimal power and in minimal Chip area.

Course Details:
•Reasons for Crosstalk

•Introduction to Noise Margin

•Crosstalk Glitch Example

•Factors Affecting Glitch Height

•AC Noise Margin

•Timing Window Concepts

•Impact of Crosstalk on Setup and Hold Timing

•Techniques to reduce Crosstalk

•Power Supply Noise

Course Curriculum

Chapter 1: Introduction

Lecture 1: Introduction

Chapter 2: Crosstalk – Why and How Crosstalk occurs in a CHIP ??

Lecture 1: High Routing Density

Lecture 2: Dominant Lateral Capacitance

Lecture 3: Introduction to Noise Margin

Lecture 4: Noise Margin Voltage Parameters

Lecture 5: Noise Margin Equation and Summary

Lecture 6: Lower Supply Voltage

Chapter 3: Glitch Examples And Factors Affecting Glitch Height

Lecture 1: Basic Crosstalk Glitch Example

Lecture 2: Glitch Discharge With High Drive Strength NMOS Transistor

Lecture 3: Glitch Discharge With High Drive Strength PMOS Transistor

Lecture 4: Factors Affecting Glitch Height – Spacing

Lecture 5: Factors Affecting Glitch Height – Aggressor Drive Strength

Lecture 6: Factors Affecting Glitch Height – Victim Drive Strength

Lecture 7: Factors Affecting Glitch Height – Conclusion

Chapter 4: Tolerable Glitch Heights and Introduction to AC Noise Margin

Lecture 1: Impacts Of Glitch

Lecture 2: Introduction to Safe and Unsafe Glitches

Lecture 3: Tolerable Glitch Heights using DC Noise Margin

Lecture 4: Tolerable Glitch Heights using DC Noise Margin Continued

Lecture 5: AC Noise Margin

Lecture 6: Impact of Load on Glitch Height

Lecture 7: Justification of Load Impact and Conclusion

Chapter 5: Timing Windows

Lecture 1: Single Victim Multiple Aggressors

Lecture 2: Introduction to Timing Window

Lecture 3: Timing Window Formation

Lecture 4: Bucketization based on Timing Windows

Lecture 5: Final Glitch Calculation

Chapter 6: Crosstalk Delta Delay Analysis

Lecture 1: Crosstalk Delta Delay – Aggressor Victim Switching in Opposite Direction

Lecture 2: Impact of Crosstalk Delta Delay on Clock Skew

Lecture 3: Setup Timing Analysis Using Real Clocks

Lecture 4: Impact of Crosstalk Delta Delay on Setup Timing

Lecture 5: Crosstalk Delta Delay – Aggressor Victim Switching in Same Direction

Lecture 6: Hold Timing Analysis Using Real Clocks

Lecture 7: Impact of Crosstalk Delta Delay on Hold Timing

Chapter 7: Noise Protection Technique

Lecture 1: Shielding

Lecture 2: Spacing

Lecture 3: Drive Strength

Chapter 8: Power Supply Noise And Power Mesh Solution

Lecture 1: Introduction To Power Supply Noise

Lecture 2: Need of Decoupling Capacitors (DECAPS)

Lecture 3: Power Supply Noise With Multiple Instantiations

Lecture 4: Voltage Droop And Ground Bounce

Lecture 5: Power Mesh Solution

Chapter 9: Summary

Lecture 1: Summary

Chapter 10: Quiz and Evaluation

Instructors

Kunal Ghosh
Digital and Sign-off expert at VLSI System Design(VSD)

Rating Distribution

1 stars: 10 votes
2 stars: 17 votes
3 stars: 65 votes
4 stars: 203 votes
5 stars: 237 votes

Frequently Asked Questions

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