VSD – Static Timing Analysis – II

Course Curriculum

Chapter 1: Introduction to sta-2 and opentimer tool

Lecture 1: Introduction to sta-2

Lecture 2: Introduction to opentimer, netlist definition and my_run.tcl creation

Chapter 2: Constraints creation commands for Opentimer

Lecture 1: Clock creation and clock arrival time definitions

Lecture 2: Input delay constraints for interface setup/hold analysis

Lecture 3: Clock slew and data slew constraints

Lecture 4: Output load and output delay constraints

Lecture 5: my_run.tcl for above experiments

Chapter 3: Full reg2reg analysis using OpenTimer tool

Lecture 1: Actual arrival time (AAT) and required arrival time (RAT) calculation basics

Lecture 2: my_netlist.v for above lecture

Lecture 3: my_netlist.timing for above lecture

Lecture 4: Slack compute, pesimissim (cppr) and engineering change order (eco)

Lecture 5: updated my_netlist.v for above lecture

Lecture 6: updated my_netlist.timing for above lecture

Lecture 7: blank.spef

Chapter 4: Interface analysis

Lecture 1: Introduction to interface analysis

Lecture 2: Case1 : C2Q and combinational delay for input is known

Lecture 3: Case2 : Input waveform specifications given

Lecture 4: Case 3 : setup_time, hold_time and combinational delay for output is known

Lecture 5: Hold fixing ECO and Case 4: Output waveform specifications known

Lecture 6: updated my_netlist.v and hold eco script for above interface analysis

Lecture 7: Case 5 : Source synchronous interface analysis for setup

Lecture 8: Source synchronous interface setup analysis in Opentimer tool

Lecture 9: Source synchronous interface hold analysis

Chapter 5: Clock gating analysis

Lecture 1: Introduction to clock gating analysis

Lecture 2: Active high clock gating analysis

Lecture 3: Active low clock gating analysis

Lecture 4: Latch based clock gating technique

Lecture 5: Integrated clock gating (ICG) cell

Chapter 6: Asynchronous and data checks

Lecture 1: Inception of asynchronous reset design technique

Lecture 2: How reset synchronizers resolves reset deassertion

Lecture 3: Data-to-data setup and hold check

Lecture 4: Sequential and clock tree min pulse width check

Chapter 7: Latch timing and load/slew analysis

Lecture 1: Introduction to positive and negative latch behavior

Lecture 2: Reg2Latch path with 'time borrow' and 'time given' examples

Lecture 3: Introduction to different kinds of power

Lecture 4: (Snippet for CTS course) Load and slew inter-dependence

Chapter 8: Conclusion

Lecture 1: Conclusion, acknowledgements and what next!!!