VSD – TCL programming – From novice to expert – Part 2

Course Curriculum

Chapter 1: Introduction

Lecture 1: Introduction

Chapter 2: Introduction to Yosys synthesis tool usage

Lecture 1: Example of a memory module RTL description

Lecture 2: Memory functionality and Synthesis using Yosys

Lecture 3: Components and Gate level netlist description of Snthesized memory

Lecture 4: Memory Write operation discussed in detail

Lecture 5: Memory Read operation and TCL scripting agenda

Chapter 3: Hierarchy check and error handling script creation for Yosys

Lecture 1: Script to do hierarchy check

Lecture 2: Demo for hierarchy check script generation

Lecture 3: Demo for error handling concept in hierarchy check

Lecture 4: Error handling script for hierarchy check

Lecture 5: Demo for error handling script

Chapter 4: Synthesis main file scripting and output file editing

Lecture 1: Synthesis script creation and demo

Lecture 2: Need and script to edit yosys output netlist

Lecture 3: Demo to edit output netlist and Introduction to 'procs'

Chapter 5: World of 'Procs'

Lecture 1: Redirect stdout proc and demo of TCL array command

Lecture 2: 'set_multi_cpu_usage' proc

Lecture 3: Demo for 'set_multi_cpu_usage' proc

Lecture 4: read_lib and read_verilog proc demo

Chapter 6: read_sdc proc – interpret clock generation constraints

Lecture 1: Read SDC file and replace square brackets by 'null'

Lecture 2: Evaluate clock period and clock port name from processed SDC

Lecture 3: Evaluate duty cycle and create clock in opentimer format

Lecture 4: Demo to convert constraints from SDC format to opentimer format

Chapter 7: read_sdc proc – interpret IO delays and transition constraints

Lecture 1: Grep clock latency and port name from SDC file

Lecture 2: Convert set_clock_latency SDC to opentimer format

Lecture 3: Demo to convert set_clock_latency in SDC to arrival_time in opentimer

Lecture 4: Script and demo convert transition and input delay to opentimer format

Lecture 5: Script and demo to convert output SDC constraints to opentimer format

Chapter 8: Process bussed ports and configuration file creation

Lecture 1: Script to expand bussed input ports for arrival time constraints

Lecture 2: Script and demo to convert all bussed constraints to bit-blasted

Lecture 3: Opentimer configuration file creation

Chapter 9: Quality of results (QOR) generation algorithm

Lecture 1: Script to obtain STA runtime

Lecture 2: Script to obtain WNS and FEP for reg2out violations

Lecture 3: Script and demo for instance count, WNS and FEP for setup and hold

Lecture 4: Script and demo for report formatting

Chapter 10: Conclusion

Lecture 1: Conclusion and acknowledgements