AXI4 Implementations in FPGA Designs

AXI4 Implementations in FPGA Designs, available at $54.99, has an average rating of 4.74, with 17 lectures, based on 35 reviews, and has 341 subscribers.

You will learn about Learn the FPGA based AXI4 Bus Protocol, including AXI4-Lite and AXI4 Stream with RTL / Verification in VHDL and Verilog AXI4 Bus signals and Master / Slave Handshaking Verification of the AXI4 Protocol and interfacing to Vendor IP Simulation Demonstrations in Verilog and VHDL with sample code files This course is ideal for individuals who are FPGA Logic designers and FPGA embedded software designers It is particularly useful for FPGA Logic designers and FPGA embedded software designers.

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Summary

Title: AXI4 Implementations in FPGA Designs

Price: $54.99

Average Rating: 4.74

Number of Lectures: 17

Number of Published Lectures: 16

Number of Curriculum Items: 17

Number of Published Curriculum Objects: 16

Original Price: $19.99

Quality Status: approved

Status: Live

What You Will Learn

Learn the FPGA based AXI4 Bus Protocol, including AXI4-Lite and AXI4 Stream with RTL / Verification in VHDL and Verilog
AXI4 Bus signals and Master / Slave Handshaking
Verification of the AXI4 Protocol and interfacing to Vendor IP
Simulation Demonstrations in Verilog and VHDL with sample code files

Who Should Attend

FPGA Logic designers and FPGA embedded software designers

Target Audiences

FPGA Logic designers and FPGA embedded software designers

A full instructional series for all aspect of the AXI4 Bus protocol, including AXI4 Stream, AXI4-Lite, and AXI4. Each flavor of AXI4 has a bus flow, handshake, and signal requirements described in detail. An example implementation for a Master and Slave in each of the subsets of AXI4 are included, with simulation demonstrations using example testbenches in edaplayground, and vivado, included using the vivado block diagram with AXI4 Protocol checking.

We learn the differences between each of the AXI4 flavors, where the AXI4 Stream protocol is used for uni-directional bulk data transfers from a master to a slave without addressing information. The AXI4 Stream protocol is the easiest to implement and the most common.

The AXI4-Lite protocol is the other common interface that we learn how to implement. We get a full understanding of how the AXI4-Lite Master handshakes with the AXI4-Lite Slave with both address and data, and allows single word writes and reads, with slave responses on valid or error transactions.

The full AXI4 protocol provides the highest data bandwith with burst modes up to 256 words of size 128 bytes. With 5 separate busses, including an Address Write Bus, a Data Write bus, an Address Read Bus, a Read Bus, and a Write Reponse bus, each with separate handshaking, there is an extensive understanding required to implement the RTL components successfully.

Course Curriculum

Chapter 1: Introduction

Lecture 1: Introduction

Chapter 2: AXI4 Stream

Lecture 1: Introduction to AXI4 Stream

Lecture 2: AXI4 Stream Slave in VHDL

Lecture 3: AXI4 Stream Slave in Verilog

Lecture 4: AXI4 Stream Master in VHDL

Lecture 5: AXI4 Stream Master in Verilog

Chapter 3: AXI4-Lite

Lecture 1: AXI4-Lite Introduction

Lecture 2: AXI4-Lite Slave in VHDL

Lecture 3: AXI4-Lite Slave in Verilog

Lecture 4: AXI4-Lite Master in VHDL

Lecture 5: AXI4-Lite Master in Verilog

Chapter 4: AXI4 Full

Lecture 1: Full AXI4 Introduction

Lecture 2: AXI4 Slave VHDL

Lecture 3: AXI4 Slave Verilog

Lecture 4: AXI4 Master VHDL

Lecture 5: AXI4 Master Verilog

Instructors

Scott Dickson
FPGA / ASIC Design Engineer

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4 stars: 9 votes
5 stars: 26 votes

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