Digital Design from Scratch
Digital Design from Scratch, available at $49.99, has an average rating of 4.3, with 33 lectures, based on 78 reviews, and has 474 subscribers.
You will learn about Digital design basics, including logic gates, binary/hexadecimal numbers, registers, shift registers, counters, timing diagrams, propagation/setup/hold timing VHDL language basics, including VHDL file formats/libraries, coding logic equations, conditional statements, arrays, timing constraints Coding, including case statements, state machines, coding from timing diagrams, while-loops, standard/unsigned types, VHDL components (modules), simulation Practical examples: memories (inferred/dual port), FIFOs, memory-mapped buses, serial interfaces (RS232, UARTs, I2C, SPI), DSP, PLLs, Manchester/8B10B encoding This course is ideal for individuals who are Entry level students interested in developing programs for FPGAs. or Technicians and engineers who would like to learn VHDL (an FPGA programming language). It is particularly useful for Entry level students interested in developing programs for FPGAs. or Technicians and engineers who would like to learn VHDL (an FPGA programming language).
Enroll now: Digital Design from Scratch
Summary
Title: Digital Design from Scratch
Price: $49.99
Average Rating: 4.3
Number of Lectures: 33
Number of Published Lectures: 33
Number of Curriculum Items: 41
Number of Published Curriculum Objects: 41
Original Price: $19.99
Quality Status: approved
Status: Live
What You Will Learn
- Digital design basics, including logic gates, binary/hexadecimal numbers, registers, shift registers, counters, timing diagrams, propagation/setup/hold timing
- VHDL language basics, including VHDL file formats/libraries, coding logic equations, conditional statements, arrays, timing constraints
- Coding, including case statements, state machines, coding from timing diagrams, while-loops, standard/unsigned types, VHDL components (modules), simulation
- Practical examples: memories (inferred/dual port), FIFOs, memory-mapped buses, serial interfaces (RS232, UARTs, I2C, SPI), DSP, PLLs, Manchester/8B10B encoding
Who Should Attend
- Entry level students interested in developing programs for FPGAs.
- Technicians and engineers who would like to learn VHDL (an FPGA programming language).
Target Audiences
- Entry level students interested in developing programs for FPGAs.
- Technicians and engineers who would like to learn VHDL (an FPGA programming language).
VHDL is a powerful programming language for developing FPGAs, but is useless without an in-depth understanding of digital design. This course provides the student a comprehensive working knowledge of both of these in parallel. VHDL describes digital logic, and, as such, is an ideal vehicle for developing a deep understanding of the functional power available in modern FPGA devices.
Course Curriculum
Chapter 1: Fundamentals
Lecture 1: 1.1: Introduction
Lecture 2: 1.2: Boolean logic gates, binary state, and timing diagrams
Lecture 3: 1.3: traffic light example, coding Boolean equations
Lecture 4: 1.4: the latch
Lecture 5: 1.5: enabled latches, series operations, and rising-edge pulses
Lecture 6: 1.6: process and conditional statements, clocked registers
Lecture 7: 1.7: register-to-register transfers, hold/setup time
Lecture 8: 1.8: elsif, enabled set/reset flop, propogation delays
Chapter 2: Functional Design Components
Lecture 1: 2.1: binary and hexadecimal numbers
Lecture 2: 2.2: shift registers, counters, vectors, and 1k vs. 1K
Lecture 3: 2.3: counter in the traffic light application, edge and terminal count detect.
Lecture 4: 2.4: coding from timing diagrams
Lecture 5: 2.5: introduction to state machines
Lecture 6: 2.6: case statements
Lecture 7: 2.7: state machines, case statements, and the traffic example
Lecture 8: 2.8: coding the simple traffic state machine
Chapter 3: FPGAs, VHDL, and simulation
Lecture 1: 3.1: introduction to FPGAs
Lecture 2: 3.2: VHDL head-on, text editors
Lecture 3: 3.3: entities and architectures, vector types, and VHDL libraries
Lecture 4: 3.4: modular design, debounce, falling-edge detection
Lecture 5: 3.5: introduction to simulation
Lecture 6: 3.6: simulation testbench, creatiing stimulus
Lecture 7: 3.7: introduction to Modelsim, constants, stalling process statements
Lecture 8: 3.8: using Modelsim
Chapter 4: Practical FPGA Elements
Lecture 1: 4.1: single and dual-port memories
Lecture 2: 4.2: arrays and while loops
Lecture 3: 4.3: inferred memories, coded dual-port memory, shared bus RAM, tri-state buffer
Lecture 4: 4.4: FIFOs
Lecture 5: 4.5: Avalon and AXI memory-mapped buses
Lecture 6: 4.6: serial interfaces, RS232, UARTs
Lecture 7: 4.7: I2C, SPI, clocks and timing
Lecture 8: 4.8: introduction to DSP
Chapter 5: Bonus: clock recovery in serial interfaces
Lecture 1: Serial interface clock recovery
Instructors
-
Blaine Readler
consulting FPGA development engineer
Rating Distribution
- 1 stars: 0 votes
- 2 stars: 0 votes
- 3 stars: 9 votes
- 4 stars: 28 votes
- 5 stars: 41 votes
Frequently Asked Questions
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