Introduction to VHDL for FPGA and ASIC design

Course Curriculum

Chapter 1: Introduction to VHDL , a first look

Lecture 1: Why VHDL

Lecture 2: First VHDL design

Lecture 3: Acquiring a VHDL simulator

Lecture 4: Download and install Altera Modelsim

Lecture 5: Vivado Simulator Demonstration

Lecture 6: Download and install Xilinx Vivado Simulator

Lecture 7: Modelsim (Altera Quartus) Demonstration

Lecture 8: Acquire and Run GHDL Simulator

Lecture 9: Simulate with EDA Playground

Lecture 10: Alternate Lab 1 Solution using Vivado

Chapter 2: Concurrent and Sequential VHDL

Lecture 1: The VHDL Process

Lecture 2: Concurrent and Sequential Statements

Lecture 3: VHDL Hierarchy

Lecture 4: Testbench Demo with Vivado

Lecture 5: Testbench Demo with Modesim

Chapter 3: RTL

Lecture 1: Understanding the Flip-Flop

Lecture 2: Synchronous Design Methodolgy

Lecture 3: RTL Styles

Chapter 4: VHDL Types

Lecture 1: Multivalue logic (std_logic)

Lecture 2: Logic Arrays and Variables

Lecture 3: State Machines

Chapter 5: VHDL Operators

Lecture 1: VHDL logical and relational operators

Lecture 2: Math Operators

Lecture 3: Functions, Procedures, and Packages

Chapter 6: Verification

Lecture 1: Verification

Lecture 2: Self Checking Testbenches