VSD – Circuit Design & SPICE Simulations – Part 1
VSD – Circuit Design & SPICE Simulations – Part 1, available at $44.99, has an average rating of 4.35, with 30 lectures, 1 quizzes, based on 592 reviews, and has 3935 subscribers.
You will learn about Understand, in brief, Physics of MOSFET Run SPICE simulations on your own and test your own circuits Get better understanding of Timing Analysis Learn VLSI from scratch to advanced (this includes my other courses as well) This course is ideal for individuals who are Anyone interested to know, what drives this $Billion VLSI industry or Anyone looking to do some practical and hands-on work on SPICE simulations or Any professional already doing Static Timing Analysis and wants to go into details of delay models or Anyone looking to stay for a long time in VLSI domain It is particularly useful for Anyone interested to know, what drives this $Billion VLSI industry or Anyone looking to do some practical and hands-on work on SPICE simulations or Any professional already doing Static Timing Analysis and wants to go into details of delay models or Anyone looking to stay for a long time in VLSI domain.
Enroll now: VSD – Circuit Design & SPICE Simulations – Part 1
Summary
Title: VSD – Circuit Design & SPICE Simulations – Part 1
Price: $44.99
Average Rating: 4.35
Number of Lectures: 30
Number of Quizzes: 1
Number of Published Lectures: 30
Number of Published Quizzes: 1
Number of Curriculum Items: 31
Number of Published Curriculum Objects: 31
Original Price: $84.99
Quality Status: approved
Status: Live
What You Will Learn
- Understand, in brief, Physics of MOSFET
- Run SPICE simulations on your own and test your own circuits
- Get better understanding of Timing Analysis
- Learn VLSI from scratch to advanced (this includes my other courses as well)
Who Should Attend
- Anyone interested to know, what drives this $Billion VLSI industry
- Anyone looking to do some practical and hands-on work on SPICE simulations
- Any professional already doing Static Timing Analysis and wants to go into details of delay models
- Anyone looking to stay for a long time in VLSI domain
Target Audiences
- Anyone interested to know, what drives this $Billion VLSI industry
- Anyone looking to do some practical and hands-on work on SPICE simulations
- Any professional already doing Static Timing Analysis and wants to go into details of delay models
- Anyone looking to stay for a long time in VLSI domain
So, you are a professional in VLSI, doing tons of tapeouts and accurate timing analysis.
OR, say, you are a student, who already went through my previous courses on clock tree synthesis, physical design flow and crosstalk,
But, sit back, and give it a thought “Have you done it all?” “Did you know, where does the delay of a cell actually comes from?” “We have learnt about delay models, but are the models accurate?” “How do you verify, if what you are doing in static timing analysis, is correct?” and many more.
These are some of curious questions we wonder about, but hardly find any answers. Even if we found the answers, as a passionate learner, we are still more curious to do some practical things on our own.
And, here’s the answer to all of them. SPICE (Simulation Program for Integrated Circuit Emphasis). This course has answers to almost all questions that you might have as a serious timing analyst
So let’s get started and keep those questions coming in the forum, and I will answer all of them.
See you in class !!
Course Curriculum
Chapter 1: Introduction to circuit design and SPICE simulations
Lecture 1: Why do we need circuit design and SPICE simulations?
Lecture 2: Introduction to basic element in circuit design – NMOS
Lecture 3: Strong inversion and threshold voltage
Lecture 4: Threshold voltage with positive substrate potential
Chapter 2: NMOS Resistive region and saturation region of operation
Lecture 1: Resistive region of operation with small drain-source voltage
Lecture 2: Drift current theory
Lecture 3: Drain current model for linear region of operation
Lecture 4: SPICE conclusion to resistive operation
Lecture 5: Pinch-off region condition
Lecture 6: Drain current model for saturation region of operation
Chapter 3: Introduction to SPICE
Lecture 1: Basic SPICE setup
Lecture 2: Circuit description in SPICE syntax
Lecture 3: Define technology parameters
Lecture 4: Standard technology file
Lecture 5: First SPICE Simulation
Lecture 6: SPICE deck for 1.2u Technology node
Chapter 4: SPICE simulation for lower nodes and velocity saturation effect
Lecture 1: SPICE simulation for lower nodes (250nm)
Lecture 2: SPICE deck for 250nm Technology node
Lecture 3: Drain current vs gate voltage for long and short channel device
Lecture 4: Id-Vgs SPICE deck for 1.2u technology node
Lecture 5: Id-Vgs SPICE deck for 250nm technology node
Lecture 6: Velocity variation at lower and higher electric fields
Lecture 7: Velocity saturation drain current model
Chapter 5: CMOS voltage transfer characteristics
Lecture 1: MOSFET as a switch
Lecture 2: Introduction to standard MOS voltage current parameters
Lecture 3: PMOS NMOS drain current v/s drain voltage
Lecture 4: Step1 – Convert PMOS gate-source-voltage to Vin
Lecture 5: Step2 & Step3 – Convert PMOS and NMOS drain-source-voltage to vout
Lecture 6: Step4 – Merge PMOS – NMOS load curves and plot VTC
Chapter 6: Conclusion and next steps
Lecture 1: Conclusion and next steps
Chapter 7: Quiz
Instructors
-
Kunal Ghosh
Digital and Sign-off expert at VLSI System Design(VSD)
Rating Distribution
- 1 stars: 9 votes
- 2 stars: 13 votes
- 3 stars: 71 votes
- 4 stars: 232 votes
- 5 stars: 267 votes
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