VSD – TCL programming – From novice to expert – Part 1

Course Curriculum

Chapter 1: Introduction

Lecture 1: Introduction to TCL task

Lecture 2: Introduction to sub-task

Chapter 2: Sub-Task One : VSDSYNTH Toolbox usage scenarios

Lecture 1: Scenario 1 – User doesn't provides input csv file

Lecture 2: Scenario 2 & 3 – User providing incorrect csv OR typing "-help"

Chapter 3: Sub-Task Two – From CSV to format[1] and SDC – Variable Creation

Lecture 1: Various tasks involved in format conversion

Lecture 2: openMSP430_design_details.csv

Lecture 3: Auto-Create variables using matrix and arrays

Lecture 4: Initialize variables for auto-creation variables task

Lecture 5: Auto creation of first variable – DesignName

Lecture 6: Auto creation of variables complete

Lecture 7: Variable Creation DEMO using TCL

Chapter 4: Sub-Task Two – From CSV to format[1] and SDC – Processing constraints,csv

Lecture 1: Checking existence of files and folders mentioned in design_details.csv

Lecture 2: Convert constraints.csv file to a matrix object

Lecture 3: Compute row number using complex matrix proccessing

Lecture 4: DEMO for computing row numbers

Chapter 5: Sub-Task Two – From CSV to format[1] and SDC – Processing clock constraints

Lecture 1: Algorithm to identify column number for clock latency constraints

Lecture 2: Start writing clock latency constraints in SDC file

Lecture 3: Complete clock latency constraints and clock slew constraints in SDC file

Lecture 4: Code to create clock constraints with clock period and duty cycle

Lecture 5: DEMO for creating complete clock constraints

Chapter 6: Sub-Task Two – From CSV to format[1] and SDC – Processing input constraints

Lecture 1: Introduction to task of differentiating between bits and bus

Lecture 2: Algorithm to categorize input ports as bits and bussed

Lecture 3: File access and pattern creation steps

Lecture 4: Regular expression and regular substitute to get fixed space strings

Lecture 5: Demo for grepping input ports from all verilogs and reformatting for fixed space

Lecture 6: Read, split, uniquify, sort and join input ports to remove duplication

Lecture 7: Evaluate length of string and Demo of bits/bussed differentiation script

Lecture 8: Demo for input constraints generation and bits/bussed differentiation

Chapter 7: Full script for download and Conclusion

Lecture 1: Constraints generation logic for output port and Conclusion!!