FPGA Embedded Design, Part 1 – Verilog

FPGA Embedded Design, Part 1 – Verilog, available at $64.99, has an average rating of 4.6, with 74 lectures, 2 quizzes, based on 1050 reviews, and has 4142 subscribers.

You will learn about Design hardware behavior with the Verilog Hardware Description Language Simulate Verilog Modules. The curriculum will take you by the hand through learning Verilog. In the series, you'll learn how to simulate your designs, how to make them real in an FPGA, and finally how to design and use your own Soft Processor This first course is about the Verilog Hardware Description Language. This is NOT a System Verilog course. However, learning Verilog is a starting point if you want to learn System Verilog (Similar to learning C prior to C++). This course is ideal for individuals who are Anyone who wants to learn FPGA design. or Arduino Makers who want to take the next step into embedded systems. or Hardware engineers who would like to learn about the exciting field of FPGA design or This course is not for experienced embedded engineers specialized in FPGAs. It is particularly useful for Anyone who wants to learn FPGA design. or Arduino Makers who want to take the next step into embedded systems. or Hardware engineers who would like to learn about the exciting field of FPGA design or This course is not for experienced embedded engineers specialized in FPGAs.

Enroll now: FPGA Embedded Design, Part 1 – Verilog

Summary

Title: FPGA Embedded Design, Part 1 – Verilog

Price: $64.99

Average Rating: 4.6

Number of Lectures: 74

Number of Quizzes: 2

Number of Published Lectures: 74

Number of Published Quizzes: 1

Number of Curriculum Items: 82

Number of Published Curriculum Objects: 81

Number of Practice Tests: 1

Number of Published Practice Tests: 1

Original Price: $199.99

Quality Status: approved

Status: Live

What You Will Learn

Design hardware behavior with the Verilog Hardware Description Language
Simulate Verilog Modules.
The curriculum will take you by the hand through learning Verilog.
In the series, you'll learn how to simulate your designs, how to make them real in an FPGA, and finally how to design and use your own Soft Processor
This first course is about the Verilog Hardware Description Language.
This is NOT a System Verilog course. However, learning Verilog is a starting point if you want to learn System Verilog (Similar to learning C prior to C++).

Who Should Attend

Anyone who wants to learn FPGA design.
Arduino Makers who want to take the next step into embedded systems.
Hardware engineers who would like to learn about the exciting field of FPGA design
This course is not for experienced embedded engineers specialized in FPGAs.

Target Audiences

Anyone who wants to learn FPGA design.
Arduino Makers who want to take the next step into embedded systems.
Hardware engineers who would like to learn about the exciting field of FPGA design
This course is not for experienced embedded engineers specialized in FPGAs.

Do you feel you’ve learned enough about microcontrollers? Do you want to learn more embedded application design techniques? How about a technique that will allow you to design high-performance systems the way professional equipment designers do?

If you’re still interested, this curriculum is for you. The FPGA Embedded Design series will teach you the exquisite art of FPGA design.

So what is an FPGA anyway?

Before moving on, let me tell you that an FPGA is not a microcontroller. It’s not a computer. Well, at least not if you don’t want it to be a microcontroller or computer.

The simplest explanation of an FPGA I’ve found is that it’s a shape shifter! It’s an integrated circuit that will behave as the logic circuit you’d like, and the way of letting it know the desired behavior is, yes, you guessed it, through programming.

But you will not do this with a Programming Language, but with a Hardware Description Language!

In this course, you’ll learn Verilog, which is one of the most widely used Hardware Description Languages (along with VHDL). You’ll learn the concurrent paradigm in the Verilog code and how to design digital systems with this powerful language. You’ll also learn that there are many purposes of an HDL: System design, simulation, implementation in either a traditional chip, or the popular FPGA alternative.

Don’t let this opportunity pass. Take the first step into the other side of embedded systems: FPGA Embedded Design.

Course Curriculum

Chapter 1: Introduction

Lecture 1: Course Structure

Lecture 2: Instructor Introduction

Lecture 3: Motivation: Hardware Design

Lecture 4: Motivation: Let's make a CPU!

Lecture 5: Motivation: CPU Design

Lecture 6: Useful Software

Chapter 2: Hardware Description Languages

Lecture 1: What exactly is a Hardware Description Language?

Lecture 2: Concurrent Design

Lecture 3: Verilog and VHDL

Lecture 4: Other HDLs

Chapter 3: [Optional] Refresher on Digital Circuit Design

Lecture 1: Digital Circuit Design

Lecture 2: Logic Gates

Lecture 3: Boolean Algebra

Lecture 4: Combinational Logic – Muxes and Demuxes

Lecture 5: Combinational Logic – Logic with Multiplexers

Lecture 6: Combinational Logic – Logic with Demultiplexers

Lecture 7: Combinational Logic – Inside Multiplexers and Demultiplexers

Lecture 8: Arithmetic with Gates

Lecture 9: Adders with Gates

Lecture 10: Sequential Logic

Lecture 11: Tri-State Buffers

Chapter 4: The Verilog Hardware Description Language

Lecture 1: Before we start…

Lecture 2: No, Wait. This is all concurrent!

Lecture 3: Verilog Code Structure

Lecture 4: Descriptive Modules

Lecture 5: Test Bench Modules

Lecture 6: Some details about Verilog

Chapter 5: Software Tutorial

Lecture 1: EDA Tools

Lecture 2: Typical Steps in EDA Suites

Chapter 6: Quick Overview of EDA Playground

Lecture 1: Creating a Playground

Lecture 2: Setting up a Playground

Lecture 3: Entering Descriptive Code

Lecture 4: Entering Test Bench Code

Lecture 5: Entering display System Tasks

Lecture 6: Simulating with display Tasks

Lecture 7: Simulating with EPWave

Lecture 8: Simulating with GTKWave

Chapter 7: Quick Overview of Modelsim

Lecture 1: Download and Installation Tips

Lecture 2: Compiling

Lecture 3: Simulation Setup

Lecture 4: Waveform Simulation

Lecture 5: More on Timescales

Lecture 6: More Features

Chapter 8: Coding Elements of Verilog

Lecture 1: Wires and Registers

Lecture 2: Number Representation: Logic Values

Lecture 3: Number Representation: Integers

Lecture 4: Logic Gates

Lecture 5: Higher-Level statements

Lecture 6: Data Assignments

Lecture 7: Multiplexers and Demultiplexers

Lecture 8: Tri-State Buffers in Veriog

Lecture 9: Tri-State Buffer Implementation in Verilog

Lecture 10: Sequential Logic

Lecture 11: Sequential Logic Example in Verilog

Lecture 12: Blocking vs Nonblocking Assignments

Lecture 13: Assignment example in EDA Playground

Lecture 14: Blocking Results

Lecture 15: Nonblocking Results

Lecture 16: Nonintuitive Results

Chapter 9: A Combinational System Example

Lecture 1: Let's make a 4-bit Adder!

Lecture 2: A Verilog Implementation

Lecture 3: Simulating with Multiple Source Files

Lecture 4: Simulation

Lecture 5: Test Bench

Lecture 6: Propagation Delays

Lecture 7: An Alternative Implementation in Modelsim

Lecture 8: Multiple Bit Signals in Modelsim

Chapter 10: A Sequential System Example

Lecture 1: Let's make an Up/Down Counter!

Lecture 2: A Verilog Implementation

Lecture 3: Simulation

Chapter 11: Wrap Up

Lecture 1: Think of all the things we learned!

Lecture 2: What's Next

Lecture 3: Farewell

Lecture 4: Bonus Lecture: LabsLand and more from Closure Labs!

Instructors

Eduardo Corpeño
Electrical & Computer Engineer
Marissa Siliezar
Telecom Engineer

Rating Distribution

1 stars: 16 votes
2 stars: 19 votes
3 stars: 142 votes
4 stars: 420 votes
5 stars: 453 votes

Frequently Asked Questions

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