Hands-On ZYNQ: Mastering AXI4 Bus Protocol

Hands-On ZYNQ: Mastering AXI4 Bus Protocol, available at $44.99, has an average rating of 3.95, with 20 lectures, based on 148 reviews, and has 1243 subscribers.

You will learn about Use Xilinx AXI4-based IP Cores Create your own AXI4-based IP Cores from scratch Create an AXI4-based Hardware Accelerator IP Core (GCD case study) Create an AXI4-based Transceiver IP Core (UART case study) This course is ideal for individuals who are Students or engineers who are working in Embedded or SoC design or Students or engineers who have a knowledge of HDL (Verilog) and C/C++ but new to AXI4 bus protocol or Students or engineers who are already using ZYNQ and want to create your own IP cores with AXI4 bus protocol It is particularly useful for Students or engineers who are working in Embedded or SoC design or Students or engineers who have a knowledge of HDL (Verilog) and C/C++ but new to AXI4 bus protocol or Students or engineers who are already using ZYNQ and want to create your own IP cores with AXI4 bus protocol.

Enroll now: Hands-On ZYNQ: Mastering AXI4 Bus Protocol

Summary

Title: Hands-On ZYNQ: Mastering AXI4 Bus Protocol

Price: $44.99

Average Rating: 3.95

Number of Lectures: 20

Number of Published Lectures: 20

Number of Curriculum Items: 20

Number of Published Curriculum Objects: 20

Original Price: $199.99

Quality Status: approved

Status: Live

What You Will Learn

Use Xilinx AXI4-based IP Cores
Create your own AXI4-based IP Cores from scratch
Create an AXI4-based Hardware Accelerator IP Core (GCD case study)
Create an AXI4-based Transceiver IP Core (UART case study)

Who Should Attend

Students or engineers who are working in Embedded or SoC design
Students or engineers who have a knowledge of HDL (Verilog) and C/C++ but new to AXI4 bus protocol
Students or engineers who are already using ZYNQ and want to create your own IP cores with AXI4 bus protocol

Target Audiences

Students or engineers who are working in Embedded or SoC design
Students or engineers who have a knowledge of HDL (Verilog) and C/C++ but new to AXI4 bus protocol
Students or engineers who are already using ZYNQ and want to create your own IP cores with AXI4 bus protocol

Note: Take this course if you want save money in training costs of similar contents. The Official Xilinx Traning Courses cost typically from 600 USD to 4000 USD. This course is not only teaches the Zynq Processing System (PS) but also the Programmable Logic (FPGA), and the interface between them.

Published (20 Apr 2019): The GCD accelerator and UART sections will be added later, and the course price will be increased, when those sections are added.

Update 1 (22 Apr 2019): English Subtitles/CCs are enabled for this course

Update 2 (02 Jan 2020): Add bonus lecture.

What is AXI?

Advanced eXtensible Interface (AXI) is an industry-standard, system bus for the connection between CPU and peripheral in System-on-Chip (SoC) design. Today AXI version 4 (AXI4) is used in many SoC that use ARM Cortex-A processors, such as Qualcomm Snapdragon, Samsung Exynos, Broadcom (used on Raspberry Pi), and many more.

What is ZYNQ?
ZYNQ is actually a SoC, not just a FPGA, because ZYNQ consists of hard processor system (ARM Cortex-A9) and programmable logic (Xilinx 7-series FPGA, equivalent to Artix-7 FPGA). The ZYNQ device enables the implementation of custom logic such as hardware accelerator in combination with software that runs on the ARM Cortex-A9. ZYNQ can also run Linux OS, which makes this device like the popular Raspberry Pi, but with FPGA inside.

This course is based on hands-on laboratory with a lot of examples. Sample codes are provided for every project in this courses.

You will receive a certificate of completion when finishing this course. There is also Udemy 30 Day Money Back Guarantee, if you are not satisfied with this course.

So, click the course button and see you inside the course.

Course Curriculum

Chapter 1: Introduction

Lecture 1: Introduction

Lecture 2: Vivado Installation

Chapter 2: ===== Part I: Use Xilinx AXI4 IP Cores =====

Lecture 1: ===== Part I: Use Xilinx AXI4 IP Cores =====

Chapter 3: Chapter1: AXI4-Lite GPIO

Lecture 1: Create the Hardware Design

Lecture 2: Test the Hardware Design using XMD

Lecture 3: Create the C Program

Lecture 4: Add the Internal Logic Analyzer IP Core

Lecture 5: Debug the Hardware Design

Chapter 4: Chapter 2: AXI4-Stream Data FIFO

Lecture 1: Simulate the Xilinx IP Core

Lecture 2: Create the Hardware Design

Lecture 3: Create the C Program

Chapter 5: ===== Part II: Create AXI4 IP Cores from Scratch =====

Lecture 1: ===== Part II: Create AXI4 IP Cores from Scratch =====

Chapter 6: Chapter 3: AXI4-Lite Shift Register

Lecture 1: Create the Shift Register in Verilog

Lecture 2: Create the AXI4-Lite Interface in Verilog

Lecture 3: Create the Hardware Design and C Program

Chapter 7: Chapter 4: AXI4-Stream Multiplier

Lecture 1: Create the AXI4-Stream Multiplier in Verilog

Lecture 2: Create the AXI4-Lite to AXI4-Stream Interface in Verilog

Lecture 3: Create the AXI4-Stream to AXI4-Lite Interface in Verilog

Lecture 4: Create the Hardware Design and C Program

Chapter 8: Bonus: Easy FPGA and Embedded Linux on ZYBO

Lecture 1: Easy FPGA and Embedded Linux on ZYBO

Instructors

Erwin Setiawan
R&D Engineer, Researcher (8000+ students)

Rating Distribution

1 stars: 2 votes
2 stars: 8 votes
3 stars: 28 votes
4 stars: 59 votes
5 stars: 51 votes

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