Hardware Description Languages for Logic Design

Hardware Description Languages for Logic Design, available at Free, has an average rating of 4.25, with 9 lectures, based on 184 reviews, and has 3582 subscribers.

You will learn about Basics of Verilog Programming This course is ideal for individuals who are Beginner of VLSI Design It is particularly useful for Beginner of VLSI Design.

Enroll now: Hardware Description Languages for Logic Design

Summary

Title: Hardware Description Languages for Logic Design

Price: Free

Average Rating: 4.25

Number of Lectures: 9

Number of Published Lectures: 9

Number of Curriculum Items: 9

Number of Published Curriculum Objects: 9

Original Price: Free

Quality Status: approved

Status: Live

What You Will Learn

Basics of Verilog Programming

Who Should Attend

Beginner of VLSI Design

Target Audiences

Beginner of VLSI Design

Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL). It is a language used for describing a digital system. Course is all about the history of the Verilog HDL language, an approach to learning Verilog, and a first phrase design example done three different ways showing the versatility of Verilog, the basics of Verilog syntax, Verilog variable values and data types, and some suggested editors that can be used to create Verilog code, how to use the assignment statements and also about the wide range of operators in Verilog and how they work, Verilog data types, what they mean and how to use them, and the difference between Nets and Registers, which are the two main data types found in Verilog, how to use modules as building blocks of Verilog circuit design descriptions, how to include an instance of another module within a module to build hierarchical designs, and two ways to instantiate a module, and which one is better, how to describe combinatorial circuits and Vera log and how to reduce Vector sizes using reduction operators, how to describe synchronous circuits in Verilog, and how to design flip-flops and latches in Verilog, how to describe basic sequence circuits and very log and how to design registers and counters in Barrel log, how to build bigger designs using modular design techniques, the use of loops in Verilog log, and how to use for Generate to make copies of circuits.

Course Curriculum

Chapter 1: Introduction

Lecture 1: First Verilog Phrase

Chapter 2: Verilog Syntax and Semantics

Lecture 1: Verilog Rules and Syntax

Lecture 2: Verilog Statements and Operators

Lecture 3: Verilog Port modes and Data types

Lecture 4: Verilog Structure

Chapter 3: Combinatorial Circuits

Lecture 1: Verilog examples for combinatioanl circuits

Chapter 4: Sequential Circuits

Lecture 1: Synchronous Circuits

Lecture 2: Synchronous sequential circuits

Chapter 5: Design in Verilog

Lecture 1: Modular Design in Verilog

Instructors

Kaithi Nirmalakumari
Engineer

Rating Distribution

1 stars: 9 votes
2 stars: 6 votes
3 stars: 41 votes
4 stars: 57 votes
5 stars: 71 votes

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