State Machines and VHDL Implementation of State Machines

Course Curriculum

Chapter 1: Introduction to State Machines and VHDL Implementation of State Machines

Lecture 1: Outline for the State Machines and VHDL Implementation of State Machines

Lecture 2: General view of State Machines, Mealy and Moore State Machines

Lecture 3: Conversion of a Mealy state machine to a Moore state machine

Lecture 4: Conversion of a Moore state machine to a Mealy state machine

Lecture 5: Designing a state machine for "011" sequence detection

Lecture 6: State machines for bit stuffing, edge detector and elevator control circuits

Lecture 7: State machines for Manchester encoding and obstacle avoidance robot are obtained

Lecture 8: State machines for RS-232 signaling, non return to zero inverted encoding

Lecture 9: VHDL Templates are given for the Implementation of State Machines

Lecture 10: Implementation of a 3-bit counter in VHDL using Moore state machines

Lecture 11: MODELSIM SIMULATION: Simulation of 3-bit counter state machine using MODELSIM

Lecture 12: Analysis of 3-bit counter state machine (in VHDL)

Lecture 13: Implementation of a Mealy state machine in VHDL

Lecture 14: MODELSIM Simulation: Simulation of Mealy State Machine Using MODELSIM

Lecture 15: Introduction to timed state machines

Lecture 16: The VHDL template for the implementation of timed state machines

Lecture 17: An example for the VHDL implementation of a timed state machine

Lecture 18: MODELSIM Simulation: Simulation of Timed State Machine